DC Balance Research Articles

Pt100 temperature measurement sensors design and transducer simulation

Abstract Temperature measurement (thermometry) is indispensable in industrial operations, aiding engineers in monitoring and evaluating temperatures. This study focuses on the utilization of Platinum Resistance Temperature Detectors (Pt100 RTDs) for precise thermal measurements, operating within an input simulation range of 0-10 V and tailored for measuring temperatures from 10°C to 90°C in chemical processes. Using the Siemens PLC300 simulation system as the power supply, the experiment involved connecting a Pt100 RTD to a DC balance Wheatstone bridge to assess thermal conductivity characteristics. The experiment in this research setup included a simulation of the circuit diagram using Multisim software, comprising a bridge configuration, amplifier circuitry, and voltage display. Results based on the Coefficient of Determination and Mean Squared Error demonstrated the sensor’s high accuracy and reliability. The experiment also underscored the importance of calibration and the impact of ambient conditions on measurement accuracy. The findings affirm the Pt100 RTD’s potential in industrial applications, offering valuable insights into its performance and areas for improvement in circuit design and component selection.

Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link

We propose an area- and power-efficient four-level pulse amplitude modulation (PAM-4) encoder/decoder for an AC coupled link system that guarantees DC balance and limited run length. Configured as 10B6Q, input data of 10 bits are mapped to 5 quaternary symbols. One of four candidate codewords that have inverted symbols at predefined positions is selected that best satisfies the requirements of DC balance and the number of transitions. One quaternary symbol is added at the end to indicate which candidate codeword is selected. This coding scheme not only guarantees the PAM-4 DC balance but also increases transition density from 75% (PRBS) to 85.6% and limits the maximum run length down to six, thus facilitating timing recovery of the receiver. Although the input data width of 10 bits is used in this implementation, the proposed scheme can be extended to wider input data with higher coding efficiency. The proposed 10B6Q encoder is fabricated in the 40 nm CMOS technology and occupies an active area of 0.0009 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a synthesized gate count of 645. It consumes 0.23 mW at the operating clock frequency of 667 MHz.

VLSI Architecture of Flexible Macroblock Ordering Manchester Encoding with Sols Method

Encoding techniques are getting the essential role of conversation. Strategies like Manchester and FM0 encoding are used as a part of numerous applications.Every strategy has distinctive activities relies upon its requirements. Every single encoding plan is utilized without losing any of its parameters. SOLS, which incorporates architecture and sync, and DSRC framework is often used to preserve the dc balance, and signal reliability is the semi-oriented logic simplification technology (SOLS). We may reduce the number of transistors and change DC by applying both procedures. The present work manages to get an incorporated design of FM0, Manchester encoding to conquer a traditional method. In this provided method, the number of hardware modules is minimized, and the total area used in Dedicated Short Reach Communication (DSRC) is consequently decreased.

Evaluation of vacuum heat-treated α-C films for surface protection of metal bipolar plates used in polymer electrolyte membrane fuel cells

Proton exchange membrane fuel cells (PEMFCs) assembled with metal bipolar plates (BPPs) is a promising power source for new energy vehicles. However, metal BPPs have serious corrosion issues and the surface electrical performance degrades in the harsh PEMFC environment. Amorphous carbon (α-C) films exhibit improved properties with both high corrosion resistance and electrical conductivity. Subsequent vacuum heat treatment of the as-coated α-C films can change their phase composition and film structure, modifying their performance. This study prepared α-C films with a titanium interlayer on a SS316L substrate by DC balance magnetron sputtering and then subjected them to vacuum heat treatment at different temperatures (400–700 °C). These treated α-C films are systemically analyzed in terms of surface and cross-sectional morphologies, sp bond hybridization, interfacial electrical conductivity, and corrosion resistance. The results indicate that the conversion of sp3 to sp2 and the compact density of α-C films are greatly enhanced with an increase in temperature, greatly improving the corrosion resistance and surface conductivity of the films. These promising results lead to a potential direction for the post-coating treatment of α-C films on metal BPPs in PEMFCs.

An Electrophoretic Display Driving Waveform Design for Reducing a Flicker and a Driving Time Based on the Fusion Optimization of Driving Stages

The speed of updating an image is very important for an electrophoretic display (EPD) application, but the flicker which can be produced among the process of updating an image is a main factor of affecting reading comfort for human eyes. In this paper, a new driving waveform, which was based on DC balance, was proposed to reduce the number of flicker and decrease the driving time for updating an image. Firstly, we studied properties of particles in the EPD, and the stages in the driving waveform were fused according to the driving properties of the particles. Secondly, an accurate reference was formed in the driving waveform for writing a new image, and the particle activity was guaranteed at the same time. Lastly, the driving waveform was downloaded to a real EPD waveform look-up table and the performance was compared with traditional driving waveforms. Experimental results showed that the proposed driving waveform could reduce flicker effectively and shorten the driving time by 25%, and an accurate white reference gray scale was obtained for displaying high quality images.

Research on Control Method of Multi-terminal Flexible DC Transmission System Based on Voltage Droop Control

Flexible DC transmission system has the advantages of small line loss, high reliability and strong controllability, and can reduce the frequency of system inactivity. In this paper, the voltage droop control method of flexible DC transmission system is studied in detail. Firstly, the principle and characteristics of the series structure, parallel structure and hybrid structure of multi-terminal flexible DC transmission system are introduced in detail. Based on this, the principle and characteristics of the control strategy of DC voltage droop control of the system are analyzed, and an improved voltage droop control strategy is proposed. Finally, a three-terminal flexible DC transmission system model is built on the Matlab/Simulink platform. The simulation results show that the control strategy plays a certain role in stabilizing DC, AC voltage, AC current and power balance control.

An SOC-Based Virtual DC Machine Control for Distributed Storage Systems in DC Microgrids

Distributed energy storage systems (DESSs) play an important role in maintaining voltage stability in DC microgrids. In order to improve the inertia of DC microgrid and balance the charge/discharge power and the state-of-charge (SOC) of each energy storage unit (ESU), an SOC-based virtual DC machine (VDCM) control strategy for DESSs in DC microgrid is proposed in this paper. By adding SOC to the armature resistance, the improved virtual machine algorithm can dynamically balance power and SOC simultaneously. In this article, the transient stability of DC bus voltage is enhanced using the output inertia of VDCM, and the SOC differences between ESUs are rapidly reduced by introducing the average SOC of ESUs. Small-signal models of both each ESU-interfacing converter and DESS-inclusive DC microgrid with proposed control method are established. The impact of VDCM parameters on voltage stability is analyzed. Finally, a test DC microgrid is built to verify feasibility and effectiveness of the VDCM control strategy.

Examination and Design of Bi-Phase Encoder for Short Range Wireless Communication

In today’s digital era, Communication systems have become ubiquitous in our everyday life. In data communication various protocols are employed to encode information bits in short range wireless communication technologies. Different types of baseband encoding schemes have been in practice for improving performance of communication which comprises of Manchester, differential Manchester and FMO codes.The transmitted signal is predicted to have zero mean for vigor issue and this is also called as dc balance. The design has been tested in Tanner EDA Tool using different logics such as CMOS logic, Pass Transistor logic and transmission gate logic.

Power Quality Improvement using Three Phase Unified Power Flow Controller (PI-Fuzzy-ANN)

Realities gadgets are utilized to control the power stream, to expand the transmission limit and to upgrade the strength of the power framework.. The controller utilized in the control instrument significantly affects controlling the power stream. As indicated by this, the capacity of UPFC is seen by utilizing distinctive control methodologies dependent on PI, fluffy rationale controllers (FLC) and fake neural system controllers in this investigation. Fluffy rationale controller is structured dependent on Mamdani's Fuzzy Inference Method while ANN depends on weighted normal method.This paper investigations the impact of controllers on execution of UPFC on the transmission lines that is liable to control quality aggravations, for example, waveform contortion and DC balance.

New Miller Codes for Run-Length Control in Visible Light Communications

Designing run-length limited codes for visible light communication systems must account for multiple performance factors, including spectral efficiency, power efficiency, dc balance, and flicker avoidance. This paper reports a new class of enhanced Miller codes, termed eMiller codes, which are capable of achieving highly desirable performances in all of these accounts. An improved Viterbi algorithm (VA), termed $mn$ VA, is developed to help further enhance the performance of eMiller codes by preserving multiple candidate sequences at each decoding stage. This performance-enhancing algorithm introduces little complexity increase compared with the original VA. Analysis on flicker control, power spectral density, and minimum Hamming distance demonstrates the all-around wellness of these new codes. Extensive simulations are carried out to evaluate eMiller codes by themselves and in practical visible light communication (VLC) systems. It is shown that the original VA already allows eMiller codes to deliver a performance noticeably better than conventional Miller and FM0/FM1 codes (and on par with Manchester codes). This result is particularly exciting, as eMiller codes are also more spectrally efficient than Manchester codes. The $mn$ VA further allows eMiller codes to surpass Manchester codes and 4B6B codes in practical RS-coded VLC systems. Simulation results confirm the superb performance of the RS-eMiller schemes.

A 100 Gbit/sec Interface for 4K/8K UHDTV Signals

A 100 Gbit/sec realtime interface has been developed specifically to transmit 4K and 8K ultrahigh-definition television (UHDTV) image formats. This 100 Gbit/sec interface can carry 8K/50p-60p/4:4:4/12-bit or 8K/100p-120p/4:2:2/10-bit image formats. The dc balance and clock recovery were secured by adopting the 8b/10b coding. A transmission distance of 2 km, the same as those of the HD/3G-SDI optical interfaces, was achieved by adopting the 1.3 $\mu \text{m}$ Quad Small Form-factor Pluggable 28 (QSFP28) optical module. The QSFP optical module has evolved and treats the data as $4\times28$ Gbits/sec. This 100 Gbit/sec interface can be the next-generation realtime interface that can cover all the 4K and 8K signal formats defined by SMPTE ST 2048–1 and ST 2036–1 as well as ST 274 and ST 296. It also maintains backward compatibility because its I/O supports HD/3G-SDI.

IoT기반 헬스케어 의료기기의 디지털 데이터 전송시간 감소를 위한 압축 바이너리 클러스터의 맨체스터 코딩 전송

This study's aim is for reducing big data transfer time of IoT healthcare devices by modulating digital bits into Manchester code including zero-voltage idle as information for secondary compressed binary cluster's compartment after two step compression of compressing binary data into primary and secondary binary compressed clusters for each binary clusters having compression benefit of 1 bit or 2 bits. Also this study proposed that as department information of compressed binary clusters, inserting idle signal into Manchester code will have benefit of reducing transfer time in case of compressing binary cluster into secondary compressed binary cluster by 2 bits, because in spite of cost of 1 clock idle, another 1 bit benefit can play a role of reducing 1 clock transfer time. Idle signal is also never consecutive because the signal is for compartment information between two adjacent secondary compressed binary cluster. Voltage transition on basic rule of Manchester code is remaining while inserting idle signal, so DC balance can be guaranteed. This study's simulation result said that even compressed binary data by another compression algorithms could be transferred faster by as much as about 12.6 percents if using this method.

VLSI DESIGN OF EFFICIENT ENCODING TECHNIQUE USING ROLS METHOD FOR WAVE APPLICATIONS

The automotive industry is emerging aggressively towards the direction of advanced active safety. The automotive industry is aiming to work for the development of Dedicated Short Range Communication (DSRC) technology, for the purpose in vehicle-tovehicle and vehicle-to-roadside communication. To transmit the vehicular information and broadcast vehicle position, DSRC communication technology is adopt as bridge. This work is devoted to develop the encoding techniques for WAVE/DSRC applications. The DSRC standards generally make use of FM0 and Manchester encoding to achieve dc balance and enhancing signal reliability. Nevertheless, the diversity of coding between FM0 and Manchester codes limits the ability to design a fully utilize hardware architecture for both. The Reuse oriented logic simplification (ROLS) technique is proposed here so that the Hardware utilization rate (HUR) will reach to 100% from 57% for both encoding techniques. The proposed architecture will have less delay, area as compared to existing architecture. In this paper the architecture analyzed to reduce the number of components. Using both encodings the area, delay, and power is reduced in DSRC. The power consumption is 22132.181nW for both encoding, and area is 193µm 2 . The encoding technique in this work supports the DSRC standards used by several organizations of America,

A Review of Manchester, Miller, and FM0 Encoding Techniques

Encoding techniques are becoming more important in communication. Techniques such as Miller, Manchester, and FM0 encoding can be used in various applications. Each technique has different operations based on their needs. Each encoding scheme should be used without losing any of its parameters. The finite state machine can be used for all encodings, because at a time the input has given the corresponding output can be occurred due to this. So speed can be increased. The fully-reused VLSI architecture of FM0, Manchester, and Miller encoders has reduced the number of transistors and maintains the DC balance. The simulation results of Xilinx indicate successful functions.

Demonstration of a 40 Gb/s Wavelength-Reused WDM-PON Using Coding and Equalization [Invited

The wavelength-division-multiplexed passive optical network (WDM-PON) has been generally regarded as a promising solution to the next-generation access network that will be required to deliver services over 40 Gb/s. However, fiber dispersion often limits the capacity and reach of WDM-PONs. Compared with dispersion compensation fiber, which is bulky and expensive with significant power loss, digital signal processing is a more suitable way to mitigate chromatic dispersion in PONs. Furthermore, expense is a critical concern in the WDM-PON, due to its need for a large number of lasers and a complex wavelength control mechanism. One practical solution is to reuse the downstream (DS) signal as the carrier for the upstream (US) modulation. In this case, the residual DS signal after remodulation can seriously degrade US transmission. In addition, system performance can be deteriorated by the unwanted reflection as uplinks and downlinks share one wavelength. In this paper, we propose using modified duobinary (MD) coding in the DS to improve its dispersion tolerance and reduce the crosstalk between DS and US induced by remodulation and reflection. MD is a correlative level code that can reduce signal bandwidth and achieve DC balance. We demonstrate a 15 km WDM-PON delivering a 40 Gb/s MD-coded signal in the downlink and a 10 Gb/s on-off keying signal in the uplink. Compared with no coding, the maximal allowable extinction ratio of the DS signal (ERd) is improved by 4 dB. Moreover, the reflection tolerance of the uplink and downlink is enhanced by 5 and 4 dB, respectively. In addition, investigations on the use of different equalizers in the DS to further suppress fiber dispersion confirm that the superior performance of nonlinear equalization in MD-coded transmission and that the network reach can be extended to 25 km by a nonlinear decision feedback equalizer.

Space vector pulse‐width modulation algorithm and DC‐side voltage control strategy of three‐phase four‐switch active power filters

A space vector pulse-width modulation (SVPWM) algorithm and a DC-side voltage control strategy for three-phase four-switch shunt active power filters are proposed. The basic principle of three-phase four-switch inverters to output three-phase balanced voltages is investigated in detail. Based on an advanced coordinate transformation, the proposed algorithm ensures basic voltage vectors to be right on the coordinate axes of αβ-coordinate system, which has the advantages of less computation and higher accuracy than the traditional. It synthesises zero vectors by equalising the duration time of two basic voltage vectors, which are equivalent in amplitude and opposite in phase, to simplify control logic and decrease harmonics of output voltages. To stabilise the DC bus voltage and balance the DC-side capacitor voltages, a DC-side voltage control strategy is presented. The former objective is obtained by controlling the active partition of the output currents, and the latter one by adapting the direct partition of phase C output current. An overall control method combining the proposed SVPWM algorithm with the DC-side voltage control strategy is presented. Experimental results have shown the validity and feasibility of the proposed algorithm and strategy.

Implementation of Encoding Circuit for Inverse Differential Manchester Code (IDMC) And Clock Recovery Circuit

In this research an inverse differential Manchester code (IDMC) circuit is implemented to encode random data using logical circuits, and clock recovery circuit is implemented too. A design of the first stage of clock recovery circuit which represents an edge detector circuit has been implemented using two one-shot mono-stable )74121( to detect the rising and falling edges respectively. The two circuits are tested practically at a low bit rate (1Kb/s) to study there operations. The encoding and clock recovery processes observed using oscilloscope. A comparison is made using simulation program (MATLAB 7.4 ) with the practical results and they were close to simulation results. The encoded circuit has been tested at (5Mb/s) which is lying in Token ring LAN range. In this research a practical illustration of the effectiveness of high pass filtering on random data has been made and compared with IDMC encoded data, this comparison improve the advantages of line code that have dc balance and high transition density which are lack in the random data. Keywords: Line Code, Inverse Differential Manchester encoder circuit, clock recovery, practical implementation

Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array

Pseudorandom single photon counting is a novel time-resolved optical measurement method, which is advantageous over convention techniques in terms of data-acquisition speed and system cost. As a critical component of the pseudorandom single photon counter, the photon arriving time digitizer should be storage efficient for a high photon counting rate, while maintaining good time accuracy. We report an ultra storage-efficient time digitizer for a pseudorandom single photon counter in this paper, which is based on the asynchronous serial communication and can store the arriving time of every photon in 1-b memory space. In addition, a novel comb-wave modulator is proposed to achieve the dc balance required for asynchronous serial communication. Our prototype implemented on field-programmable gate arrays provides a time resolution of 400 ps. It can register up to 4.2-Giga photon arriving time tags with 1024 × 32-b memory space.

Design of Multigigabit-per-Second Transceiver for Band-Limited High-Speed Data Communication Using DC-Free Signaling

This paper presents a 5-Gb/s transceiver for AC-coupled interconnects using de-free signaling based on symbol-rate-carrier offset quadrature phase-shift-keying modulation. A modified Costas loop for the clock and data recovery is also proposed to perform the receiver function. Without the need of an encoding scheme for dc balance, the proposed modulation can be used in high-speed ac-coupled high-speed interconnect systems. The theory and analysis of the proposed dc-free signaling are discussed in this paper. The fully integrated transmitter and the receiver are implemented using a 0.18-mum CMOS technology. Measurement results demonstrate the transmitted 5-Gb/s data can be successfully recovered by the receiver chip after an ac-coupled FR4 printed circuit board transmission line of up to 20 in. The transceiver consumes 200 mW from a 1.8-V power supply.

The Silicon Backplane Design for an LCOS Polarization-Insensitive Phase Hologram SLM

Polarization-insensitivity is achieved in a reflective spatial light modulator by laying a quarter-wave plate (QWP) at the incident wavelength directly over the mirror pixels of a silicon backplane, and forming a nematic Freedrickcz cell over the QWP to modulate the reflected phase. To achieve the highest drive voltage from the available silicon process, a switched voltage common front electrode design is described, with variable amplitude square wave drive to the pixels to maintain constant root-mean-square drive and minimize phase fluctuations during the dc balance refresh cycle. The silicon has been fabricated and liquid-crystal-on-silicon cells both with and without the QWP assembled; applications include optically transparent switches for optical networks, beam steering for add-drop multiplexers for wavelength-division-multiplexing telecommunications, television multicast, and holographic projection.