dBm Saturated Output Power Research Articles

Design of a broadband high‐efficiency extended resistive continuous Class‐B/J power amplifier with novel drain voltage waveforms

AbstractThis article presents an extended resistive continuous broadband Class‐B/J (ERCB/J) power amplifier (PA) that incorporates two newly designed parameters in the drain voltage waveform. The incorporation of these newly designed parameters enables the PA to achieve a lower degradation rate of efficiency and output power over a wide bandwidth. To validate the effectiveness of the proposed method, a PA was designed, fabricated, and measured. The PA adopting commercially available GaN high electron mobility transistor technology operates from 1.0 to 3.0 GHz, exhibiting a fractional bandwidth of 100%. Across this frequency range, the PA delivers more than 39.6 dBm of saturated output power and more than 62% of drain efficiency. The measured results show good agreement with theoretical analysis and simulation, confirming the validity of the proposed method.

Area Efficient and Linear MMIC Based Ka Band Power Amplifier for 5G Communication Systems

This work presents a monolithic microwave integrated circuit (MMIC) based power amplifier (PA) with single 150 nm GaN high electron mobility transistor (HEMT) using broadband matching. For the proposed amplifier, two stage L-type biasing network is designed. In order to provide good linearity, low Q, broader bandwidth and optimized chip area, band pass filter (BPF) type matching network is proposed. The topology and parameter selection is done by performing proper load pull analysis. This helps in achieving wide band matching to maintain low Q factor. Thus the proposed amplifier is evaluated with post layout EM simulation data. For the 26 GHz band of 5G communication, proposed amplifier has a small signal gain of 11 dB for 21-27.4 GHz. The amplifier offers 33.42 dBm saturated output power and good linearity. The designed PA provides 31.35 dBm output power, 26% power added efficiency (PAE) and 29% drain efficiency (DE) at 1 dB compression with IP3 of 39.67 dBm for 26 GHz band. The designed PA has less complexity and small chip area of 4.3 mm2.

Highly Efficient GaN Doherty Power Amplifier for N78 Sub-6 GHz Band 5G Applications

In this paper, a high-efficiency GaN Doherty power amplifier (DPA) for 5G applications in the N78 sub-6 GHz band is introduced. The theoretical analysis of the matching networks for the peak and carrier transistors is presented, with a focus on the impact of unequal power splitting for both transistors and the recommendation of a post-harmonic suppression network. The proposed design features an unequal Wilkinson power divider at the input and a post-harmonic suppression network at the output, both of which are crucial for achieving high efficiency. The Doherty power amplifier comprises two GaN 10 W HEMTs, measured across the 3.3 GHz to 3.8 GHz band (the N78 band), and the results reveal significant improvements in gain, output power, drain efficiency, and power-added efficiency. Specifically, the proposed design achieved a power gain of over 12 dB and 42 dBm saturated output power. It also achieved a drain efficiency of 80% at saturation and a power-added efficiency of 75.2%. Furthermore, the proposed harmonic suppression network effectively attenuated the harmonics at the output of the amplifier from the second to the fourth order to more than −50 dB, thus enhancing the device’s linearity.

A Wideband Power Amplifier in 65 nm CMOS Covering 25.8 GHz–36.9 GHz by Staggering Tuned MCRs

Broadband millimeter-wave power amplifiers have attracted much attention and have wide applications for 5G communication, satellite communication, radar, sensing, etc. Yet, it is challenging to design a power amplifier with broadband small-signal gain and power performance simultaneously. In this study, a transformer-based symmetrical magnetically coupled resonator (MCR) matching network for broadband output matching and stagger-tuned MCRs are used to achieve both broadband small- and large-signal performance. Also, to enhance the gain for the power amplifier, a three-stage common-source pseudo-differential structure is adopted to mitigate the low-gain issue due to stagger tuning, and the shunt resistors aimed to decrease the Q factor of the MCRs. We used the in-phase two-way current combined with microstrip transmission lines to increase the output power. Designed in 65 nm bulky CMOS technology, the power amplifier presents a 3 dB small-signal gain bandwidth from 25.8 GHz to 36.9 GHz, indicating a peak gain of 25.87 dB at 30.5 GHz. The power amplifier demonstrates a 17.84 dBm saturated output power (Psat) at 31 GHz and a 24.37% peak power added efficiency (PAEmax) at 28 GHz. The power amplifier achieves a flat Psat of 17.44 ± 0.4 dBm, a PAEmax of 22.59 ± 1.78%, and an OP1dB of 13.78 ± 0.31 dBm from 26 GHz to 36 GHz.

A two-way three-stage W-band power amplifier with series-parallel inductor-based T-type inter-stage matching network

A two-way three-stage W-band power amplifier (PA) in 65 nm CMOS SOI process (Ft/Fmax: 120 GHz/220 GHz) is presented in this paper. A differential cascode structure with a series-parallel inductor-based T-type inter-stage matching network is proposed to improve efficiency and power gain near three quarters of Ft. A high passive efficiency transformer-based two-way parallel power combining output matching network is implemented to increase the output power and achieve compact layout. The proposed W-band PA achieves a post-layout simulated 22.1-dB small-signal power gain (S21) and 7.2-GHz 3-dB bandwidth from 90.9 to 98.1 GHz. The post-layout simulated large-signal performances of the PA shows it achieves 17.11 dBm saturated output power (Psat), 13.68 dBm output 1-dB compression point (OP1dB) and 11.15% peak power-added efficiency (PAE) at 94.5 GHz.

A Ka-Band SiGe BiCMOS Quasi-F−1 Power Amplifier Using a Parasitic Capacitance Cancellation Technique †

This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power amplifier (PA). A detailed methodology for the evaluation of the active device’s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting in enhanced performance. A simplified model for the extraction of time-domain intrinsic voltage and current waveforms at the output of the main active core is introduced, enforcing the implementation process of the proposed quasi-inverse class F technique. The PA is fabricated in a 130 nm SiGe BiCMOS technology with fT/fmax=250/370 GHz and it is suitable for 5G applications. It achieves 33% peak power-added efficiency (PAE), 18.8 dBm saturation output power Psat, and 14.7 dB maximum large-signal power gain G at the operating frequency of 38 GHz. The PA’s response is also tested under a modulated-signal excitation and simulation results are denoted in this paper. The chip size is 0.605×0.712 mm2 including all pads.

A 39 GHz Dual-Channel Transceiver Chipset with an Advanced LTCC Package for 5G Multi-Beam MIMO Systems

A 39-GHz dual-channel CMOS transceiver chipset with an advanced LTCC packaging and the demonstration of a proposed dynamic multi-beam architecture based on the chipset for 5G MIMO applications. This article presents a 39 GHz transceiver front-end chipset for 5G multi-input multi-output (MIMO) applications. Each chip includes two variable-gain frequency-conversion channels and can support two simultaneous independent beams, and the chips also integrate a local-oscillator chain and digital module for multi-chip extension and gain-state control. To improve the radio-frequency performance, several circuit-level improvement techniques are proposed for the key building blocks in the front-end system. Furthermore, an advanced low-temperature co-fired ceramic process is developed to package the 39 GHz dual-channel transceiver chipset, and it achieves low packaging loss and high isolation between the two transmitting (TX)/receiving (RX) channels. Both the chip-level and system-in-package (SIP)-level measurements are conducted to demonstrate the performance of the transceiver chipset. The measurement characteristics show that the TX SIP provides 11 dB maximum gain and 10 dBm saturated output power, while the RX SIP achieves 52 dB maximum gain, 5.4 dB noise figure, and 7.2 dBm output 1 dB compression point. Single-channel communication link testing of the transceiver exhibits an error vector magnitude (EVM) of 3.72% and a spectral efficiency of 3.25 bit·s −1 ·Hz −1 for 64-quadrature amplitude modulation (QAM) modulation and an EVM of 3.76% and spectral efficiency of 3.9 bit·s −1 ·Hz −1 for 256-QAM modulation over a 1 m distance. Based on the chipset, a 39 GHz multi-beam prototype is also developed to perform the MIMO operation for 5G millimetre wave applications. The over-the-air communication link for one- and two-stream transmission indicates that the multi-beam prototype can cover a 5–150 m distance with comparable throughput.

A Wideband Balanced Amplifier Using Edge-Coupled Quadrature Couplers in 0.13-μm SiGe HBT Technology

In this work, a wideband millimeter-wave (mm-wave) power amplifier (PA) is reported. To provide excellent input/output impedance matching across broadband, sufficient output power and high power-added efficiency (PAE), a balanced amplifier (BA)-based architecture is used in designing this PA. In particular, an edge-coupled quadrature coupler is designed as its RF-power-division/combination block, and its performance in terms of magnitude/phase balance error is minimized throughout a relatively wide bandwidth. A PA prototype is fabricated in 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe HBT technology and tested. Under a 1.6-V power supply, the variation of small-signal gain is less than 3 dB within 20-40 GHz, which is equivalent to more than 66% fractional 3-dB bandwidth. Within this frequency range, at least 15.8 dBm saturated output power could be delivered with the peak PAE higher than 16.8%. The designed PA supports a single-carrier 200-MHz 64-quadrature amplitude modulation (QAM) with higher than 12.8-dBm average output power, while still maintaining an error vector magnitude (EVM) below −25 dB at 30 GHz. The size of the designed compact-size PA, including all pads, is only 0.7 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1.3$ </tex-math></inline-formula> mm.

An Efficient 24-30 GHz GaN-on-Si Driver Amplifier Using Synthesized Matching Networks.

This paper presents a broadband GaN microwave monolithic integrated circuit driver amplifier (MMIC DA) with compact dimensions of 1.65 mm × 0.78 mm for 5G millimeter-wave communication. The optimal impedance domain satisfying the preset goals was first acquired using the simplified load-pull procedure and small-signal simulations, followed by a weighted average method to determine the reference center matching point from which the optimal intrinsic load can be deduced. By means of de-embedding load-pull contours, modeling based on theoretical analysis, and simulation fitting for parameter identification, the nonlinear output capacitance and a series RLC model circuit approximating the input impedance response of the stabilized transistor were extracted. Under the design principle of fully absorbing the parasitic parameters of the device, explicit formulas and tabulated methods related to the Chebyshev impedance transformer were applied to construct filter-based synthesized matching networks at each stage and finally convert them into an implementable mixed-element form via the single-frequency equivalence technique. Measured on-wafer pulsed results for the proposed two-stage DA across 24-30 GHz demonstrated up to 31.1 dBm of saturated output power (Psat) with less than 1 dB total fluctuation, 19.3 ± 1 dB of small-signal gain, and 39.8% of peak power-added efficiency (PAE) at the mid-frequency.

A novel stair‐finger grid type transistor for high‐performance millimeter‐wave power amplifier

A novel stair-finger grid type (SFGT) transistor layout is proposed in this letter to improve the f T ${f}_{{\rm{T}}}$ and f max ${f}_{\max }$ of large-sized transistors for the millimeter-wave power amplifier (PA). It combines the promoted stair-finger transistor cells in a grid pattern to minimize parasitic capacitances and metal losses, which has been verified to provide higher gain over broadband by measurements. Two three-stage dual-differential PAs with different transistor layouts are compared in this letter. The PA employs a capacitive neutralization technique and distributed active transformer-based combiner and divider. Fabricated in the Huali Microelectronics Corporation (HLMC) 40-nm Complementary Metal Oxide (CMOS) (Co process, the PA with SFGT transistor [PA2] achieves higher gain and output power than the PA with the currently best-known transistor [PA1]). PA2 achieves 15.22 dBm saturated output power ( P sat ${P}_{\mathrm{sat}}$ ), 14.25 dBm output power at 1 dB compression point ( P 1 dB ${P}_{1\unicode{x0200A}\mathrm{dB}}$ ), and 18.09 dB power gain when the basic supply is 1.1 V at 83 GHz.

A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications

ABSTRACT A fully integrated 2-transmitter–4-receiver (2TX–4RX) multiple-input multiple-output (MIMO) radar front-end in the 57–64-GHz band for short-range applications is presented in this paper. The proposed architecture with 8 elements within a one-dimensional virtual array enables theoretical angular resolution down to . The TX chains operate in time-division multiplexing (TDM) mode, and each delivers 12 dBm of saturated output power with output-referred 1-dB compression point (OP1dB) larger than 5 dBm over 7-GHz bandwidth. The millimeter-wave (mm-wave) part of the RX chains has a noise figure lower than 13 dB, and a conversion gain of 17 dB in the 60-GHz unlicensed band. The receiver chain shows a maximum conversion gain of 77 dB, while achieving an input-referred 1-dB compression point (IP1dB) greater than – 12.5 dBm, including baseband circuitry. The programmable baseband processing chain with 60-dB gain allows beat frequency selection in the frequency range from 100 kHz up to 1.3 MHz. Linear chirps are synthesized using a fractional-N phase-locked loop (PLL) with a fundamental voltage-controlled oscillator (VCO). The integrated system includes a programmable multiplying delay-locked loop (MDLL) which scales-up external high purity 40-MHz frequency reference to a referent 240-MHz clock used in the frequency-modulated continuous-wave (FMCW) synthesizer. The front-end is implemented in a 130-nm SiGe:C BiCMOS process. The chip occupies an area of 12 mm2 including pads and consumes 930 mW, combined from 1.2-V and 3.3-V supplies.

Broadband High-Efficiency Quasi-Class-J Power Amplifier Based on Nonlinear Output Capacitance Effect

In this brief, a broadband high-efficiency quasi-Class-J power amplifier (PA) based on nonlinear output capacitance effect is proposed. With the influence of the voltage across between drain and source ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{v}_{\mathrm{ DS}}$ </tex-math></inline-formula> ) at the over-driven condition, the negative second harmonic termination has been generated by the nonlinear output capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{C}_{\mathrm{ out}}$ </tex-math></inline-formula> ). Since the proposed PA is driven into saturation, the current magnitude can be increased which improves the output power and efficiency. Meanwhile, the fundamental termination is modulated near the real axis of the Smith chart by the second harmonic termination, which reduces the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> -factor to extend the bandwidth. It is possible to achieve the saturated PA working in the wide frequency band. Finally, the proposed PA shows a relatively high performance of greater than 39.6 dBm saturated output power, and delivers an average of 64 % drain efficiency (DE) from 3.5 to 5.5 GHz.

Design of a High-Efficiency Doherty Power Amplifier for 5G Applications Using Wilkinson Power Divider

In this paper, a novel Doherty Power Amplifier DPA based on a 10 W gallium-nitride high-electron-mobility transistor (GaN-HEMT) technology is designed using Advanced Design System (ADS) software. In the design, two different single Power Amplifiers (PAs) are combined using a Wilkinson power divider which is also used to connect the power to the load. The designed DPA operates in the range of 2.0-3.0 GHz and aims to achieve high efficiency, wide bandwidth and high output power for 5G applications. Simulation results showed a 40% fractional bandwidth and more than 44 dBm of saturated output power. In addition, the Power-Added Efficiency (PAE) and Drain-efficiency (Deff) are about 77% and 84%, respectively. A comparison with the other previous works shows enhancement in the maximum large-signal gain (L_S_Gain) in the average of 2.5 dB and an average PAE of about 10%. This improvement can be attributed to the deployment of the power divider/combiner proposed in the design and also the optimization of the components during the design.

Dual‐mode linearity enhanced power amplifier with wideband AM‐PM compensation for 5–6‐GHz FeLAA applications

This letter presents a 5–6-GHz dual-mode power amplifier (PA) realized for further enhanced licensed assisted access application of downlink transmission. The output matching network with multiple harmonic traps and the wideband AM-PM compensation technique are used in the design. To achieve high linear output power with less variation in the wide frequency range, different bias voltages of the first stage PA are set for dual-mode operation. In the range 5–6 GHz, the PA delivers > 30 dBm saturated output power and reaches 24.4–24.8 dBm linear power at −35 dBc adjacent channel leakage ratio.

Extending the L-band amplification to 1623 nm using Er/Yb/P co-doped phosphosilicate fiber.

The gain bandwidth of the erbium-doped fiber amplifier limits the enhancement of the transmission capacity in optical fiber communication systems. This Letter reports an erbium-ytterbium co-doped phosphosilicate fiber, which is expected to increase transmission capacity by extending the L-band gain bandwidth to 1623 nm. The fiber was fabricated by modified chemical vapor deposition combined with solution doping technology. The mechanism of bandwidth-expansion by inhibiting the signal excited-state absorption was investigated. When the signal power and pump power were maintained at -3.7dBm and ∼720mW at 1480 nm, the 20 dB gain range was extended out to 1623 nm. Additionally, the noise figure at 1623 nm decreased to 6.01 dB, with 23 dBm saturated output power. The results show that the erbium-ytterbium co-doped phosphosilicate fiber has a great potential for extending L-band amplification.

Design of broadband high-gain GaN MMIC power amplifier based on reactive/resistive matching and feedback technique

This paper presents a K-band two-stage power amplifier (PA) with a compact circuit size of 1.8×0.87mm2. To guarantee broadband high-gain output performance, the optimal impedance domain and power cell are determined through load/source-pull simulation and K-point method, respectively. Reactive/resistive matching networks are carefully employed to reduce the equivalent gate capacitance, improve stability and compensate for the device’s negative gain roll-off slope. Meanwhile, combining with feedback technique adopted in driver stage, the entire operation bandwidth can be further extended. Under 12V pulse voltage supply, 37.4% of peak power-added efficiency (PAE) at 26GHz and 24±0.5dB of small-signal gain, 30.3-31.6dBm of saturated output power (Psat) across 22-27GHz are obtained as shown in the experimental results.

Design of a Wideband Doherty Power Amplifier with High Efficiency for 5G Application

This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off.

Multibeam Phased-Arrays Using Dual-Vector Distributed Beamforming: Architecture Overview and 28 GHz Transceiver Prototypes

This article presents a dual-vector distributed beamformer architecture that employs a series-feed network and is capable of supporting up to four simultaneous beams. The multibeam array uses scalar functions within each front end to create Cartesian-weighted signals needed for phase shifting. A dual-vector series-feed network combines/distributes these signals for the receiver/transmitter whereas a global quadrature interpolator is used to create two conjugate beams. By using an interpolator on either end of the series feed, a total of four beams can be obtained. Among these four beams, a first beam can be controlled independently, a second beam is formed as an image of the first, a third beam is offset from the first based on the amount of phase shift within the series-feed structure, and a fourth beam is an image of the offset beam. In this work, the theory of operation of the series-feed DVDB is presented and then two different four-element 28 GHz DVDB transceiver array prototypes in 120 nm SiGe BiCMOS technology are described. One uses a hybrid coupler for global interpolation at radio frequency (RF) and the other uses quadrature mixers for global interpolation at baseband. Measurement results for the array employing passive interpolation at RF show excellent phase-shifting performance, including < 1 dB root-mean-squared (RMS) gain error, < 2 degree RMS phase error, 24% 3 dB bandwidth, with 16–18.6 dBm saturated output power in transmit mode and 4.9–7.3 dB noise figure in receive mode. Measurement results for the array employing mixer-based interpolation likewise show excellent phase-shifting performance with similar RMS gain and phase errors and slightly degraded overall RF performance. Comparing the two, we conclude that the DVDB with passive interpolation at RF is better suited for partitioned systems where beamformers and transceivers are realized on separate chips to support larger, scalable arrays. In contrast, the DVDB with mixer-based interpolation is better suited for integrated systems where beamformers and frequency translation functions must be integrated together.

A 4–20 GHz, multi‐watt level, fully integrated push–pull distributed power amplifier with wideband even‐order harmonic suppression

This study presents the first fully integrated, push–pull, high power distributed amplifier (DA) for wideband applications in 0.25 µm Gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process. A triple-stacked field-effect transistor cell is employed for each stage of the DA along with the non-uniform distributed power amplifier topology to maximise the output power. The experimental results show that the amplifier exhibits from 7 to 10 dB gain with vi30–32 dBm output power at 1 dB compression (P1 dB) and 32–35.4 dBm saturated output power (Psat) covering a frequency bandwidth from 4 to 20 GHz. The measured second harmonic suppression is >33 dBc from 8 to 40 GHz at the P1 dB operating condition.

A novel design method for extending power back‐off range of broadband Doherty power amplifier

AbstractIn this article, a novel design method for extending the output back‐off (OBO) range of the Doherty power amplifier (DPA) is proposed. The influence of the power ratio of the peaking and carrier power amplifier on the bandwidth of the DPA is analyzed in detail. With the proposed theory, the simplified estimation of the bandwidth of the DPA for a specific OBO range can be carried out. A broadband high‐efficiency DPA working from 1.8 to 2.6 GHz (33% relative bandwidth) with 9 dB OBO level is designed to verify the proposed method. According to the measured results, the DPA achieves 44.6 to 46.8 dBm saturation output power and drain efficiency (DE) of 61% to 74%. And at 9 dB OBO level, the DE varies from 50% to 63% over the operation band. Furthermore, digital predistortion (DPD) measurement results show that the linearized DPA can meet the spectral requirements for modern wireless communication systems.