dBm Output Research Articles

A High Power Density Ku‐Band GaN Power Amplifier Based on Device‐Level Thermal Analysis

ABSTRACTThis paper introduces a new design method for a high‐power density GaN MMIC amplifier operating in the Ku‐band. A thermal model to investigate the thermal distribution of power amplifiers is proposed to achieve optimal performance in terms of power density, chip size, and channel temperature. The thermal distribution and channel temperature of a single device, an eight‐way parallel device combination, and the entire PA layout are obtained by finite element simulation. The thermal coupling effects of high‐power MMICs are analyzed in detail. The thermal resistances are extracted from the simulation to design a Ku‐band amplifier. Measurement results demonstrate that the designed amplifier achieves 43.0–44.2 dBm output power and 22.7%–34.5% PAE at 28 V drain voltage with a 100 μs pulse width and 10% duty cycle within 12–18 GHz. The proposed design method enables the amplifier to have a compact layout of 10.88 mm2 and a power density between 1.84 and 2.42 W/mm. This design method can offer valuable insights for future development of high‐power MMIC amplifiers.

Design of a Series of Inverse Continuous Modes Power Amplifier Based on Bandpass Filter

ABSTRACTIn this paper, a broadband high‐efficiency power amplifier (PA) with filtering characteristics is proposed. This PA is designed using a series of inverse continuous modes (SICMs) and adds a novel coupled microstrip line filter structure. The terminal of this structure is composed of microstrip lines cascaded to improve the out‐of‐band suppression effect. This filter can achieve low in‐band insertion loss, high passband selectivity, as well as deep stopband rejection performance simultaneously. A PA was designed and implemented using a 10 W GaN HEMT device, verifying its wideband characteristics. The measurement result shows that the 39.6–41.6 dBm output power (Pout), 61.6%–73.7% drain efficiency (DE), and 8.6–10.8 dB gain are achieved at 2.2–2.9 GHz.

A 114–126-GHz Frequency Doubler With >10 dBm Output Power and >12% Efficiency in 45 nm RFSOI

A 114–126-GHz Frequency Doubler With >10 dBm Output Power and >12% Efficiency in 45 nm RFSOI

Quantum dot fourth-harmonic colliding pulse mode-locked laser for high-power optical comb generation

Quantum-dot mode-locked lasers have advantages such as high temperature stability, large optical bandwidth, and low power consumption, which make them ideal optical comb sources, especially for wavelength-division multiplexing (WDM) telecommunications, and optical I/O applications. In this work, we demonstrate an O-band quantum dot colliding pulse mode-locked laser (QD-CPML) to generate optical frequency combs with 200 GHz spacing with maximum channels of 12 within 3 dB optical bandwidth. To achieve the high output power of individual comb lines, four channel conditions are implemented at central wavelength of 1310 nm for WDM transmission experiments. Each channel exhibits more than 10 dBm output power with 200 Gb/s PAM-4 and 270 Gb/s PAM-8 modulation capability via thin-film LiNbO3 Mach–Zehnder interferometer modulator without the requirement of any optical amplifications. This high-order QD-CPML is an ideal comb source for power-efficient optical interconnects and large bandwidth optical data transmission.

A 60 GHz low phase noise VCO with second harmonic tail extraction in 40-nm CMOS

This work presents a 60 GHz continuously adjustable mm-wave cross-coupled voltage − controlled oscillator (VCO) utilizing an innovative frequency doubling technique in 40 nm CMOS technology. The extraction of the second harmonic is performed through a transformer from the tail of the 30 GHz fundamental VCO. The primary side of the transformer serves a dual purpose, functioning both as a filter for the second harmonic and as a balun simultaneously. The circuit incorporates a MOS varactor along with a four-bit binary weighed capacitor bank to achieve coarse and fine frequency tuning respectively. Post Layout simulation results indicate that the VCO spans a broad tuning range of 12.3 GHz, covering frequencies from 52.7 to 64.98 GHz. Phase noise (PN) remains below −96.3 dBc/Hz at a 1 MHz frequency offset within all bands Power consumption, including the output stage, is 21.8 mW from a 1.1-Volt supply. The VCO provides more than −13 dBm output power in all frequency bands and occupies a chip area of 0.53 mm2.

3.3-4.3 GHz efficient continuous class-F gallium nitride power amplifier based on simplified real frequency technique and harmonic tuning.

In order to implement the fifth generation (5G) communication system for a large number of users, the governments of many countries nominated the low 5G frequency band between 3.3 and 4.3 GHz. This paper proposes a wideband RFPA by designing the input matching network (MN) and output MN of the device using the simplified real frequency technique (SRFT) and the harmonic tuning network. The load-pull and source-pull is applied at multiple points for 100 MHz intervals over the bandwidth to obtain the optimum impedances at the output and input of the 10W Gallium Nitride (GaN) Cree CGH40010F device. To verify the design, the RFPA is simulated, and the performance is measured between 3.3 and 4.3 GHz. According to experimental findings, the measured drain efficiency (DE) throughout the whole bandwidth ranged from 57.5 to 67.5% at the output power of 40 dBm. Moreover, at the 1 dB compression point between 39.2 and 42.2 dBm output power, the drain efficiency (DE) achieves a high value of 81.2% with an output power of 42.2 dBm at a frequency of 3.3 GHz. The RFPA can obtain a maximum gain of 12.4 dB at 3.5 GHz. The linearity of the RFPA with a two-tone signal is measured and the value is less than -22 dBc all over the band.

Millimeter-Wave GaN High-Power Amplifier MMIC Design Guideline Considering a Source via Effect

A millimeter-wave (mmWave) gallium nitride (GaN) high-power amplifier (HPA) monolithic microwave-integrated circuit (MMIC) was implemented, considering a source via effect. In this paper, we introduce guidelines for designing GaN HPA MMICs, from device sizing to meeting high-power specifications, power matching considering source via effects, schematic design of three-stage amplifier structures, and electromagnetic (EM) simulation. Based on the results of load pull simulation and small-signal maximum stable gain (MSG) simulation, the GaN high-electron-mobility transistor (HEMT) size was selected to be 8 × 70 μm. However, since the source via model provided by the foundry was significantly different from the EM results, it was necessary to readjust the power matching considering this. Additionally, when selecting the source via size, the larger the size, the easier the matching, but since the layout of the peripheral bias circuit is not possible, a compromise was required considering the actual layout. To prevent in-band oscillation, an RC parallel circuit was added to the input matching circuit, and low-frequency oscillation was solved by adding a gate resistor on the PCB module. The proposed PA was fabricated with a commercial 0.1 μm GaN HEMT MMIC process. It exhibited 38.56 to 39.71 dBm output power (Pout), 14.2 to 16.7 dB linear gain, and 14.1% to 18.2% power-added efficiency (PAE) in the upper Ka band. The fabricated GaN power amplifier MMIC shows competitive Pout in the upper Ka band above 33 GHz.

A 46% PAE, 2.4-GHz Two-Stage Class E Power Amplifier Utilizing CMOS 0.13-µm Technology

A wireless device with a long battery life and great sensitivity becomes difficult to develop since there is a huge demand for low-power, low-cost wireless gadgets. The power amplifier (PA) is the most crucial part of radio frequency (RF) transceivers because of its massive power consumption. Consequently, in order to minimize power loss, a very effective and low-power consumption PA is needed. In this paper, high efficiency two-stage CMOS PA designed in 0.13-μm process for 2.4 GHz IoT transmitter applications is presented. The driver stage and power stage are the two stages that make up the two-stage topology of the proposed CMOS PA. To attain high efficiency and great power gain, a class E PA is used at the power stage. The LC matching network at the output is used for harmonic rejection filter at 2.4 GHz with an additional parallel capacitor helps for better harmonic rejection. In addition, a layout has been successfully designed and optimized. All the components in the proposed PA are designed on-chip. The pre-layout and post-layout simulations have been conducted to verify the proposed PA's performance. The pre-layout simulation of the proposed PA can deliver 19.19 dBm output power and 45.2% PAE at 2.0 V power supply into a 50-Ω load. On the other hand, the proposed PA produced an output power of 17.33 dBm and 46% PAE, according to the results of the post-layout simulation with a similar power supply of 2.0 V. The chip area for the proposed layout design is 1.05 mm2.

Input‐harmonic manipulated wideband high‐efficiency series of continuous mode power amplifier

SummaryIn this paper, a systematic research of the effects of second source harmonics caused by gate‐source capacitance in the design of a series of continuous mode (SCM) power amplifiers (PAs) is first presented. The research results show that, compared to the conventional SCMs that require the input second harmonic to be short circuited, SCMs under the impact of input nonlinearity have a more flexible input second harmonic manipulation space, and to further improve and maintain the performance of PAs in wideband operations, a new impedance design space is explored through analysis. For practical validation, SCMs PA considering the effects of the input nonlinearity is designed and fabricated with a 10‐W gallium nitride (GaN) device, acquiring 39.1–42 dBm output power and 60.6–71.5% drain efficiency (DE) performance at a 3 dB gain compression level operating over the 0.5–3.5 GHz frequency range with a relative bandwidth of 150%.

A concise high‐efficiency broadband parallel‐circuit Class‐E power amplifier

SummaryAn analysis of a single‐ended high‐efficiency broadband parallel‐circuit (PC) Class‐E power amplifier (PA) with a single reactance compensation technique (RCT) and low‐pass (LP) Chebyshev impedance transformer is first presented under low supply voltage. Analysis of the gate and drain voltage allows to determine the required optimum voltage values for the expected PA design objectives. Derivation and design procedure of the broadband matching network (MN) is provided, which can effectively filter out higher order harmonics and reduce circuit complexity. In addition, the load adaptability for this PA is studied, achieving higher than 67.87% drain efficiency (DE) in the case of load mismatch. A PC Class‐E PA based on NMOS transistor is designed and implemented to validate the analysis over a frequency band of 7–9.4 MHz. Experimental results show that the PA delivers 36.48–38.83 dBm output power with a DE of 84.91% to 86.91%, as well as achieves 83.98% to 86.28% power‐added efficiency (PAE), 19.48–21.83 dB gain with a low supply voltage of 12 V. It is also demonstrated that the experimental results exhibit good agreement with the simulation results, which prototype the radio frequency identification transmitter with broadband high‐efficiency and system compactness. To the author's knowledge, this study represents the first approach to design broadband PC Class‐E PA under low supply voltage for Internet of Things (IoT) applications at HF frequency band, such as electronic article surveillance (EAS) system.

Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler

This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm2 and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.

N77 Radio Frequency Power Amplifier Module for 5G New-Radio High-Power User Equipment Mobile Handset Applications

This paper presents a highly efficient 5G New-Radio (NR) RF power amplifier module (PAM). The n77 PAM consists of a high-voltage differential-topology 2 μm GaAs HBT power amplifier, a CMOS controller, a silicon-on-insulator (SOI) switch, an integrated passive device (IPD) bandpass filter, a low-noise amplifier (LNA), and a bi-directional coupler. This PAM generates a saturation output power of 32.7 dBm including the loss of the SOI switch and output filter. The designed n77 PAM is tested with a commercial envelope tracker IC (ET-IC). The designed PAM with an ET-IC achieves an ACLR of −37 dBc at a 27 dBm output power with a DFT-s-OFDM QPSK 100 MHz NR signal and saves a dc power consumption of 950 mW compared to the APT mode. For the CP-OFDM 256QAM with the most stringent EVM requirements, it achieves an EVM of 1.22% at 23 dBm and saves 640 mW compared to the APT mode.

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

Area Efficient and Linear MMIC Based Ka Band Power Amplifier for 5G Communication Systems

This work presents a monolithic microwave integrated circuit (MMIC) based power amplifier (PA) with single 150 nm GaN high electron mobility transistor (HEMT) using broadband matching. For the proposed amplifier, two stage L-type biasing network is designed. In order to provide good linearity, low Q, broader bandwidth and optimized chip area, band pass filter (BPF) type matching network is proposed. The topology and parameter selection is done by performing proper load pull analysis. This helps in achieving wide band matching to maintain low Q factor. Thus the proposed amplifier is evaluated with post layout EM simulation data. For the 26 GHz band of 5G communication, proposed amplifier has a small signal gain of 11 dB for 21-27.4 GHz. The amplifier offers 33.42 dBm saturated output power and good linearity. The designed PA provides 31.35 dBm output power, 26% power added efficiency (PAE) and 29% drain efficiency (DE) at 1 dB compression with IP3 of 39.67 dBm for 26 GHz band. The designed PA has less complexity and small chip area of 4.3 mm2.

A new approach for ultra-wideband continuous class B/J power amplifier design and fabrication based on increasing efficiency in power loss-less case

A new theoretical approach to designing an ultra-wideband continuous class B/J power amplifier is presented. In the conventional design of continuous class J, the maximum accessible bandwidth is limited to one octave, which is equivalent to 66 % fractional bandwidth. In this paper, it will be shown by reforming the voltage expression of resistive-reactive class J, high efficiency continuous class B/J power amplifier design can be realized sothat the output power level maintains across more than one octave. Using a new defined correction factor in the output voltage of resistive-reactive class J while the third harmonic element with a proper coefficient is added to it, not only could help to decrease the compromise between the design space and efficiency but also improve the PA output power than conventional one. To check the feasibility of the suggested approach and validate the theoretical and simulation results, a broadband PA using CGH40010F GaN transistor in 0.5–2 GHz is designed and fabricated on RO4003c substrate with 20 mil thickness. The measured 39.8–42.2 dBm output power with 63.68 % average drain efficiency over more than 120 % fractional bandwidth confirmed both the theoretical and simulation results.

An efficient microwave outphasing transmitter based on class-E power amplifiers

This article presents two alternative topologies combining lumped and distributed elements for designing class-E power amplifiers (PAs) for the 3.5 GHz frequency band, that differ in their approach to terminating the second harmonic. The first design employs a transmission line with a capacitor to create a short-circuit, while the second design uses a simple stub. The first design outperforms the second one in terms of efficiency enhancement. Accordingly, an outphasing transmitter based on a surface mount hybrid coupler combiner is designed using the first topology, achieving peak value results of 78% drain efficiency and 44.3 dBm output power. At a 6 dB back-off point, the simulation results show that the proposed architecture achieves 67.6% drain efficiency.

Ka-band stacked and pseudo-differential orthogonal load-modulated balanced power amplifier in 22 nm CMOS FDSOI

Abstract This paper presents an integrated power amplifier (PA) following the orthogonal load-modulated balanced amplifier (OLMBA) topology. The fixed-phase prototype in this paper is implemented with 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon-on-insulator (FDSOI) process. The proposed PA operates at 26 GHz frequency range, where it achieves 19.5 dBm output power, 16.6 dB gain, 15.7% power added efficiency, and 18.3 dBm output 1-dB compression point ( $P_{\rm 1\,dB}$ ). The PA is also tested with high dynamic range modulated signals, and it achieves, respectively, 11.4 dBm and 4.9 dBm average output power (Pavg) with 100 MHz and 400 MHz 64-QAM third-generation partnership project/new radio frequency range 2 signals, and 14 dBm Pavg with 0.6 Gb/s (120 MHz) single carrier 64-QAM signal, measured at 26 GHz and using −28 dBc adjacent channel leakage ratio and −21.9 dB (8%) error vector magnitude as threshold values. The proposed OLMBA is also compared to a stand-alone quadrature-balanced PA. Modulated measurements show that the stand-alone quadrature-balanced PA has better linearity in deep back-off, but the OLMBA has better efficiency.

W‐band ×8 frequency multiplier in 65 nm CMOS with 25% bandwidth and 4.63 dBm output power

AbstractThis letter presents an ×8 frequency multiplier for the W‐band wireless satellite communication in the 65 nm complementary metal‐oxide‐semiconductor process. To reduce the power consumption, the proposed frequency multiplier employs only one driven amplifier and three stages of doublers. All doublers adopt balanced structures to increase their robustness. The output buffer is introduced to ameliorate the impedance matching of output port so that the output power of the proposed ×8 frequency multiplier can achieve 4.63 dBm. Through the special design of the interstage impedance matching circuit, the relative 3‐dB bandwidth of the proposed frequency multiplier is over 25% (from 74.8 to 96.2 GHz). The chip also has a small size and low power consumption, which is 1.37 × 0.51 mm2 and 125 mW, respectively.

A new continuous Class‐E mode based on the general theory of high‐efficiency continuous power amplifier

SummaryBy multiplying with the continuous factor (CF), the conventional Class‐ , Class‐J power amplifier (PA) can be expanded to their corresponding continuous modes, resulting in a great degree of freedom for broadband design. However, this method can hardly apply to other types of PAs. In view of this problem, the continuous mode is deeply analyzed from the perspective of equation solving for the first time, and a general theory for high‐efficiency broadband continuous PA design is proposed. In this theory, the continuous impedance space does not rely on a mapping relationship achieved by multiplying with the CF, but on a direct solution of the high‐efficiency equations to obtain the broadband design space. This approach is simpler and has the potential to provide greater design space. As a validation, this theory is used for the analysis of Class‐E PAs and a new continuous Class‐E (NC‐E) PA is presented. With knee‐point voltage and finite harmonics taken into account, this type of PA greatly expands the broadband design space of Class‐E PAs and also has the advantage of harmonic matching. The NC‐E PA is designed and manufactured using GaN HEMT CGH40010F, which achieves 40.6–41.6 dBm output power and 66.2%–74.2% drain efficiency (DE) in the frequency band of 2.5–3.8 GHz.

Design of a 0.4–3.9-GHz Wideband High-Efficiency Power Amplifier Based on a Novel Bandwidth Extended Matching Network

The design of a multi-octave power amplifier (PA) is presented based on extended continuous Class-B/J (ECB/J) modes in this paper. The wide design space provided by the ECB/J modes has been used as the goal for the design. A unique bandwidth extended matching network that can achieve a broadband impedance matching in the appropriate impedance region by simultaneously manipulating six frequency points is proposed to compensate for the impedance dispersion effect caused by the change of the optimal impedance with the operating frequency in the design of the matching network. To verify the proposed methodology, a wideband PA is designed and fabricated by using a commercial 10-W gallium nitride (GaN) device. The implemented PA achieves a bandwidth of 163% from 0.4 to 3.9 GHz while exhibiting excellent performance of 38-42.3 dBm output power, 57-68% drain efficiency, and 10-13 dB gain. The measured adjacent channel power ratio (ACPR) is lower than -26 dBc at 0.8, 1.5, 2.0, 2.5, 3.0, and 3.5 GHz when the output power is lower than 36 dBm.