dBm OIP3 Research Articles

Design and Test of Innovative Three-Couplers-Based Bandpass Negative Group Delay Active Circuit

An innovative design method of bandpass (BP) negative group delay (NGD) active circuit is developed. The BP NGD topology consists originally of octopole and hexapole coupled line (CL) couplers. The NGD active circuit is validated by a prototype implemented in hybrid technology. The measured results are in good agreement with simulations. The CL-based passive circuit generates BP NGD performance with simulated and measured results showing NGD level of approximately -12 ns having 1.97 GHz center frequency with -11 dB transmission coefficient and -16 dB reflection coefficient. To compensate the loss, active circuit was fabricated by cascading the passive circuit with a microwave amplifier. Subsequently, the previous BP NGD performance is achieved with 0 dB gain. Moreover, a notable active microwave device characterization is performed with the NGD prototype via nonlinear measurements. It was found that the tested NGD prototype operates with 10-dB noise figure, 21 dBm P1dB compression, 29 dBm and 41 dBm OIP3.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

PurposeThe purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).Design/methodology/approachThe linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.FindingsWith this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.Practical implicationsThe proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.Originality/valueThe proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

38-GHz CMOS Linearized Receiver With IM3 Suppression, P 1 dB/IP3/RR3 Enhancements, and Mitigation of QAM Constellation Diagram Distortion in 5G MMW Systems

This article proposes a 35–39-GHz high linearity in-phase and quadrature components receiver (I/Q Rx) using a 65-nm CMOS for quadrature amplitude modulation (QAM) carrier demodulation in 5G millimeter wave (MMW) systems. An innovative cold-bias transistor passive mixer core with low local oscillator (LO) power is proposed. Built-in MMW linearizers are adopted in the low-noise amplifier (LNA) and downconverter to improve the linearity with significant third-order intermodulation (IM3) power suppression in a wide RF/IF power range for QAM demodulation. According to the Rx measurement at 38 GHz, it exhibits the −13 dBm IP1dB/0.8 dBm OP1dB and 2 dBm IIP3/16.8 dBm OIP3 with the highest IM3 reduction of 31 dB. The maximum output (IF) power with a third-harmonic rejection ratio (RR3) lower than −40/−30 dBc is −4.7/−2 dBm, which exhibits a superior IM3 suppression capability at high power level. Moreover, QAM constellation diagram (CD) distortions due to IM3 interferences of the Rx in high RF/IF power are investigated. Experiments verify that distorted CDs are recovered by using the proposed linearizers. To the best of the authors’ knowledge, the proposed Rx exhibits the highest IF linear power with RR3 ≤ −30 dBc compared to the published Rxs/downconverters and is the first MMW linearized Rx that demonstrates an ability to mitigate QAM CD distortions.

A 0.49–13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3

A novel switched-capacitor low-pass filter architecture is presented. In the proposed scheme, a feedback path is added to a charge-rotating real-pole filter to implement complex poles. The selectivity is enhanced, and the in-band loss is reduced compared with the real-pole filter. The output thermal noise level and the tuning range are both close to those of the real-pole filter. These features make the filter suitable for high speed, low noise, and low power applications. A fourth-order filter prototype was implemented in a 180-nm CMOS technology. The measured in-band loss is reduced by 3.3 dB compared with that of a real-pole filter. The sampling rate of the filter is programmable from 65 to 300 MS/s with a constant dc gain. The 3-dB cut-off frequency of the filter can be tuned from 490 to 13.3 MHz with over 100-dB maximum stop-band rejection. The measured in-band third-order output intercept point is 28.7 dBm, and the averaged spot noise is 6.54 nV/√Hz. The filter consumes 4.3 mW from a 1.8 V supply.

An X-Band SiGe BiCMOS Triple-Cascode LNA With Boosted Gain and P1dB

In this brief, the design, implementation, and experimental results of an X-band low noise amplifier (LNA) implemented in 0.13 $\boldsymbol \mu \text{m}$ SiGe BiCMOS process technology is reported. The presented LNA based on an inductively degenerated triple-cascode topology employing SiGe hetero-junction bipolar transistors (HBT) featuring ${f} _{\textbf {T}}/{f} _{\textbf {max}}$ of 250/330 GHz. To authors’ best knowledge, this brief is the first LNA incorporating triple-cascode topology and HBTs. Design techniques explored to enhance the gain, noise figure (NF), and linearity performance, along with the investigation of advantages provided by utilizing triple-cascode configuration are addressed. The measurement of the proposed LNA results in a minimum NF of 1.35 dB at 8 GHz, which remains less than 1.7 dB across 6–12 GHz frequency band. In addition, the LNA delivers a peak gain of 20.5 dB at 9 GHz, where it exhibits a state-of-the-art output 1-dB compression point (OP1dB) of 18.75 dBm and third-order intercept point OIP3 of 24.75 dBm, while drawing 21 mA dc current from a 4.8-V supply. According to the utilized figure-of-merit, the measured results are better compared to previously reported work in the open literature.

10 GHz highly linear up‐conversion mixer in 65 nm CMOS

A highly linear folded-type up-conversion mixer working at 10 GHz is presented. The mixer utilises a feedback loop to linearise the gm stage and make the effective gm only determined by a resistor theoretically. Moreover, the effects of local oscillator (LO) power levels on the circuit DC condition and linearity performances are examined from both the theoretical analysis and measurement results. The mixer prototype, fabricated in a 65 nm CMOS technology, consumes 7.7 mW from 1.2 V supply voltage and exhibits 13.4 dBm OIP3 at the LO power of 2 dBm.

A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

This letter presents a CMOS wideband variable gain LNA for 28-GHz 5G integrated phased-array transceivers preserving high third-order intercept point (OIP3) at all gain settings. The prototype LNA has three stages providing digitally controlled gain optimized for higher IIP3 at lower gain. The stages are coupled together using double-tuned transformers for maximum group delay flatness. Fabricated in a 40-nm CMOS process, it achieves 18–26 dB gain at 1-dB gain step with 12–14.5 dBm OIP3 and 3.3–4.3 dB noise figure, while consuming 21.5–31.4 mW across 26–33 GHz frequency range. The root-mean-square error of the gain steps is less than 0.38 dB.

A Low Noise Amplifier with 1.1dB Noise Figure and +17dBm OIP3 for GPS RF Receivers

A 1.575GHz SiGe HBT(heterojunction bipolar transistor) low-noise-amplifier(LNA) optimized for Global Positioning System(GPS) L1-band applications was presented. The designed LNA employed a common-emitter topology with inductive emitter degeneration to simultaneously achieve low noise figure and input impedance matching. A resistor-bias-feed circuit with a feedback resistor was designed for the LNA input transistor to improve the gain compression and linearity performance. The LNA was fabricated in a commercial 0.18µm SiGe BiCMOS process. The LNA achieves a noise figure of 1.1dB, a power gain of 19dB, a input 1dB compression point(P1dB) of -13dBm and a output third-order intercept point(OIP3) of +17dBm at a current consumption of 3.6mA from a 2.8V supply.

A 0.4 V Microwatt Power Consumption Current-Reused Up-Conversion Mixer

This letter proposes a novel up-conversion mixer with pseudo-differential and current-reused topology in 90 nm CMOS technology. The proposed source-pumped up-conversion mixer can operate at near weak inversion under a power consumption of 149 μW from a 0.4 V supply voltage while maintains acceptable circuit performance at millimeter-wave (MMW) frequencies. Measurement results show that the up-conversion mixer exhibits a -0.62 dB conversion gain (CG) and a -4 dBm OIP3. An achieved figure-of-merit (FoM) is 1.46.

An 8-W 250-MHz to 3-GHz Decade-Bandwidth Low-Noise GaN MMIC Feedback Amplifier With > +51-dBm OIP3

This paper describes a GaN monolithic microwave integrated circuit (MMIC) cascode feedback amplifier design which achieves up to 8 W of output power and greater than +51 dBm OIP3 across a 250-3000-MHz decade bandwidth. The LNA also achieves 20 dB of flat-gain across the band. The design was fabricated with a 0.25-μm GaN HEMT technology with an fT ~ 50 GHz and a BVgd >; 60 V. A 40-V 750-mA high-bias LNA design achieves an OIP3 of 51.9 dBm, P1dB of 38.5 dBm, and NF ~ 3 dB at 2 GHz . A 40-V 500-mA medium-bias LNA design achieves a lower NF ~ 2.5 dB , an OIP3 of 48.4 dBm, and a P1dB of 36.8 dBm at the same frequency. At an optimum low-noise bias of 20 V and 300 mA, a NF ~ 0.96 dB, an OIP3 of 43.4 dBm, and a linear P1dB of ~32.2 dBm was also obtained. The combination of high OIP3 and low NF from these GaN MMIC LNA designs exceed that achieved by many state-of-the-art PHEMT, HBT, and HFET technologies for decade-BW MMIC amplifiers operating in the popular wireless and wire-line S- and C-band frequency ranges. The linear GaN LNA performance demonstrated here can enable new generations of software-defined and reconfigurable radios which require ultra-linearity over multiple octaves of bandwidth.

An Improved Broadband High Linearity SiGe HBT Differential Amplifier

An improved all-npn broadband highly linear SiGe amplifier is presented. The operation of the proposed amplifier relies on two dependent translinear loops. The frequency response, linearity, input voltage swing range, and noise performance are analyzed. A broadband linear amplifier with 46 dBm OIP3 at 20 MHz, 34 dBm OIP3 at 1 GHz, 6 dB noise figure, and 10.3 dBm output P1 dB is demonstrated.

Novel directional coupled waveguide photodiode–concept and preliminary results

A novel photodiode is presented using a directional coupler incorporated with a UTC style photodiode with 0.88 A/W responsivity and 35 dBm OIP3 at 25 mA. The device responsivity is characterized at various photocurrents up to 10 mA and the OIP3 is measured up to 25 mA and 10 GHz. Additionally, the device capacitance is measured and used to model the capacitance limited OIP3 of the device. The failure of the device was compared to a traditional waveguide photodiode showing burnout no longer occurs at the front of the device and demonstrated the potential of the new design to control the photocurrent density profile for a waveguide style photodiode.

A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

In this paper, a differential-ramp based variable gain amplifier (VGA) technique is introduced. Using the proposed technique, digitally programmable gain amplifiers (PGAs) can be converted to analog controlled, dB-linear VGAs with minimum impact on noise and linearity. This provides an efficient way of realizing an analog controlled VGA for OFDM based applications. The technique is illustrated by converting an opamp based high-linearity, low-noise PGA to a dB-linear VGA for CMOS mobile TV applications. The design including the cascade of a two-stage continuous 65-dB-linear VGA and a third-order Sallen-Key buffer stage is fabricated in a 65 nm CMOS process. The measured in-band OIP3 of the whole chain at maximum gain of 47 dB is 22 dBm, whereas the blockers in the adjacent channel result in 34 dBm OIP3 for the same gain setting. The design achieves 11 nV/?(Hz) input referred noise density and occupies a die area of 0.17 mm2. The VGA circuit consumes 1.5 mA of current from a 1.2 V supply with an additional 200 ?A switch control ramp current from a 2.5 V supply.

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.