dBc Adjacent Channel Leakage Ratio Research Articles

A 6-/12-dB back-off reconfigurable Doherty-like load modulated balanced amplifier with compact area and wide bandwidth

This article presents a Doherty-like Reconfigurable Load Modulated Power Amplifier (R-LMBA) topology, which enables a broadband 6-/12-dB power back-off (PBO) reconfiguration by rearranging the bias voltages of the sub-amplifiers with compact area. The proposed R-LMBA guarantees proper phase differences among the three sub-PAs across the entire operating frequency band without the need for a bulky phase shifter that is adopted in conventional LMBAs. The design equations for the R-LMBA are proposed and analyzed in detail. A proof-of-concept PA has been designed in 0.1 μm GaAs pHEMT process to verify the proposed concept. In Mode-1, from 30 to 40 GHz, it achieves saturated output power (Psat) of 27.7–29.1 dBm with peak power added efficiency (PAE) of 28.5–34.4%, and 16.8–22.1% PAE at 6-dB PBO with its best 1.29 × efficiency enhancement over a Class-B counterpart. In Mode-2, it exhibits 28 dBm Psat with 30% peak PAE, and a PAE of 25%/13.6% at 6-/12-dB PBO, which is 1.67 × /1.81 × over an ideal Class-B PA. Besides, in Mode-1/-2, the PA demonstrates 21.3/20.3 dBm average output power (Pavg) and 17.9%/22.1% average PAE (PAEavg) with −28.1/-23.8 dB error vector magnitude (EVM) and −29.1/-25.9 dBc adjacent channel leakage ratio (ACLR) under 6-Gb/s 64-QAM modulated signal at 35 GHz.

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

Ka-band stacked and pseudo-differential orthogonal load-modulated balanced power amplifier in 22 nm CMOS FDSOI

Abstract This paper presents an integrated power amplifier (PA) following the orthogonal load-modulated balanced amplifier (OLMBA) topology. The fixed-phase prototype in this paper is implemented with 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon-on-insulator (FDSOI) process. The proposed PA operates at 26 GHz frequency range, where it achieves 19.5 dBm output power, 16.6 dB gain, 15.7% power added efficiency, and 18.3 dBm output 1-dB compression point ( $P_{\rm 1\,dB}$ ). The PA is also tested with high dynamic range modulated signals, and it achieves, respectively, 11.4 dBm and 4.9 dBm average output power (Pavg) with 100 MHz and 400 MHz 64-QAM third-generation partnership project/new radio frequency range 2 signals, and 14 dBm Pavg with 0.6 Gb/s (120 MHz) single carrier 64-QAM signal, measured at 26 GHz and using −28 dBc adjacent channel leakage ratio and −21.9 dB (8%) error vector magnitude as threshold values. The proposed OLMBA is also compared to a stand-alone quadrature-balanced PA. Modulated measurements show that the stand-alone quadrature-balanced PA has better linearity in deep back-off, but the OLMBA has better efficiency.

A 35 dBm PSAT and 41% PAE GaAs Power Amplifier With Series Distributed-Balun

This brief presents a high-power Sub-6 GHz two-way differential power amplifier (PA) with a series distributed-balun output network in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5{\mu }\text{m}$ </tex-math></inline-formula> GaAs pHEMT process. The proposed series distributed-balun output network consists of two coupled-line-based distributed-baluns connected in series to achieve low-loss matching and power combining. The general three-port distributed-balun unit and its extended two-way series distributed-balun have been theoretically analyzed in detail. In addition, the multi-layer transformer structure is introduced to enhance the coupling factor of the inter-stage matching network. The measurement results of this three-stage PA demonstrate a peak gain of 32.6dB, with 3-dB bandwidth (BW−3dB) of 4.2-6 GHz. The saturated output power (Psat) is 34–35 dBm covers 4.8-6 GHz, and the peak power-added efficiency (PAE) is 41%. The measured root mean square error vector magnitude (EVMrms) with 160MHz of 64-QAM/256-QAM is 2.4%/1.93% with 28.7/26.5 dBm average output power (Pave) and −36.8/−38.7 dBc adjacent channel leakage ratio (ACLR) without digital pre-distortion (DPD).

A temperature‐compensated linear GaAs HBT power amplifier for small‐cell applications in −25 to 125∘C$^\circ \rm C$ lunar environment

A two-stage 920–960 MHz power amplifier (PA) in GaAs heterojunction bipolar transistor (HBT) process is demonstrated for small-cell communications in the lunar environment. To cope with the temperature fluctuations during lunar days, a novel complementary to absolute temperature (CTAT) biasing scheme is proposed for the PA to achieve an ultra-wide-range temperature compensation. Moreover, to meet the linearity requirements of the small-cell applications while producing high output power, a band-stop filter is employed in the biasing circuit of the second stage to reduce the AM– AM distortions. Over the temperature range of −25 to 125°C, the PA is capable of operating for the small-cell applications over a gain ranging from 30.2 to 32.8 dB. The proposed PA achieves 24.5 dBm linear power with −47 dBc adjacent channel leakage ratio (ACLR) and a PAE of 15%.

Dual‐mode linearity enhanced power amplifier with wideband AM‐PM compensation for 5–6‐GHz FeLAA applications

This letter presents a 5–6-GHz dual-mode power amplifier (PA) realized for further enhanced licensed assisted access application of downlink transmission. The output matching network with multiple harmonic traps and the wideband AM-PM compensation technique are used in the design. To achieve high linear output power with less variation in the wide frequency range, different bias voltages of the first stage PA are set for dual-mode operation. In the range 5–6 GHz, the PA delivers > 30 dBm saturated output power and reaches 24.4–24.8 dBm linear power at −35 dBc adjacent channel leakage ratio.

Fully integrated three-way LDMOS Doherty PAs for 1.8–2.2 GHz dual-band and 2.6 GHz m-MIMO 5G applications

AbstractThis paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems.

Inphasing Signal Component Separation for an X-Band Outphasing Power Amplifier

This work investigates signal component separator design for an RF-input outphasing power amplifier (RFIO PA). In the RFIO architecture, the phase- and amplitude-modulated input signals to the outphasing power stage are realized using a nonlinear “inphasing” network, resulting in an outphasing system that operates on a single RF input. Previous RFIO work has demonstrated the feasibility of this approach, but the combined nonlinear effects of the inphasing and outphasing networks have resulted in overall poor linearity. In this work, we use a simplified transistor model to predict the inphasing network design requirements, and then compare three nonlinear components to synthesize the required transfer function. An $X$ -band monolithic microwave-integrated circuit (MMIC) in 150-nm GaN is used as the output stage, and its operation is characterized for hybrid inphasing networks based on three different technologies: diode-connected HEMT, p-i-n diode, and nonlinear GaN mesa resistor. The RFIO PA with mesa resistor inphasing network achieves a linearity-efficiency compromise with −27.9 dBc adjacent channel leakage ratio (ACLR) and 29% PAE at an average output power of 27.7 dBm for a 100-MHz long-term evolution (LTE) signal with 7.9 dB peak-to-average power ratio (PAPR) centered at 10 GHz.

Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation

In this paper, we present a design technique for broadband fully integrated GaN power amplifiers (PAs), with merged bandpass filter (BPF) and AM-PM compensation. The minimum-inductance BPF structure is used as the output matching network of the PA. A new theory of the minimum-inductance BPF is developed and it is shown that, compared to the standard BPF, it can be implemented using lower total inductance and provide higher out-of-band attenuation. Furthermore, using a two-transistor architecture, an AM-PM compensation technique is proposed where compressive and expansive nonlinearity profiles of the transistors' transconductance and gate-source capacitance are combined to achieve a linear total transconductance and input capacitance, over a wide power range. A fully integrated PA prototype, implemented in a 0.25-μm GaN-on-SiC process with 28-V supply, provides 35.1-38.9dBm output power, 45-61% drain efficiency (DE), 40-55% power-added efficiency (PAE), and 11.3-13.4dB power gain, across 2.0-4.0GHz. For a 256-QAM signal with 7.2-dB PAPR and 100-MHz bandwidth at 2.4GHz, it achieves 2.5% (-32.0dB) rms error vector magnitude (EVMrms) and -37.5/-37.6dBc adjacent channel leakage ratio (ACLR), while average output power and DE/PAE are respectively 30.1dBm and 20.6/19.5%, without predistortion. EVMrms and ACLR can be improved to 0.5% (-46dB) and -46.4/-46.8dBc by using digital predistortion (DPD).

A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters

We present a broadband dual-channel power amplifier (PA) with crosstalk suppression for multi-input multi-output (MIMO) communications. Operation of MIMO system with crosstalk is theoretically evaluated for two popular coding schemes including the space-time coding and linear precoding. Design challenges of a multi-channel PA on a single chip are investigated and circuit techniques, including second-harmonic trapping integrated into the output matching network and the use of back-via lines to isolate the channels, are proposed to mitigate the inter-channel crosstalk. A fully integrated dual-channel PA prototype, implemented using a 250-nm GaN-on-SiC process, provides 34.9–36.3dBm output power, 44–49% power-added efficiency (PAE), 11.3–12.3 dB power gain, 31.0–34.2 dB second-harmonic rejection, and −28.1 dB to −25.7 dB inter-channel crosstalk across 4.5–6.5 GHz. For a 100-MHz 256-QAM signal with 7.2 dB peak-to-average power ratio (PAPR), the PA achieves 29.9dBm average output power, 30% average PAE, −38.2/−39.1 dBc adjacent channel leakage ratio (ACLR), and −28.2 dB (3.9%) rms error vector magnitude (EVM), without using digital predistortion (DPD). Effect of crosstalk on linearity of the dual-channel PA is also measured and it is shown that for a 256-QAM signal EVM can increase by 3–8 dB, depending on relative power levels of the two channels.

A Fully Integrated Reconfigurable Multimode Class-F2,3 GaN Power Amplifier

In this letter, we propose a reconfigurable multimode fully integrated power amplifier (PA) in GaN technology. The PA is composed of one main transistor, biased in class-AB, and three auxiliary transistors which can be switched between class-AB and deep class-C, to improve efficiency and linearity of the PA. Furthermore, a harmonic termination network is proposed to enable the operation of the PA in class-F2,3. A proof-of-concept PA, fabricated using a 250-nm GaN-on-SiC process, provides 33.8-dBm output power and 42% peak drain efficiency (DE) at 4.8 GHz. Modulated-signal measurements using a 200-MHz 256-QAM 7.2-dB peak-to-average power ratio (PAPR) signal indicate that rms error vector magnitude (EVMrms) of < 5% (−26 dB) can be achieved with 27.7–28.5 dBm average output power, 26%–30% average DE, and −38.1 to −33.5 dBc adjacent channel leakage ratio (ACLR), in the four operation modes. It is shown that ACLR can be improved by 6 dB at lower output power levels through reconfiguring the mode of PA operation.

A CMOS Highly Linear Doherty Power Amplifier With Multigated Transistors

This paper presents a highly linear and power back-off efficiency-enhanced Doherty power amplifier (PA) fully integrated into CMOS. The proposed Doherty PA employs a transformer-based quadrature signal generator, multigated transistors (MGTRs) in the main PA, Class-C mode auxiliary PA, and synthesized transformer-based Doherty parallel output network with the second-harmonic control circuits. An on-chip 8-port transformer-based quadrature signal generator is designed within a single transformer footprint ( $340\,\,\mu \text{m}\,\,\times 340\,\,\mu \text{m}$ ) and provides 0°/−90° differential signals to the main/auxiliary PAs. The MGTR in the main PA is implemented using four transistors with different sizes and biases to generate and extend a near-zero $\text {g}_{\text {m3}}$ operation region. Moreover, an on-chip transformer-based Doherty parallel output network with the second-harmonic control circuits shows higher passive efficiency compared with a conventional Doherty parallel output network and provides low second-harmonic loads to the main/auxiliary PAs. Both the proposed MGTR in the main PA and the second-harmonic control circuits in the main/auxiliary PAs suppress the third-order intermodulation distortion of the Doherty PA. This results in a substantial linearity improvement of the Doherty PA, which can support high-order modulation signals and reduce or even eliminate the need for digital predistortion (DPD). As a proof-of-concept design, a 5.8 GHz Doherty PA is implemented in a standard 55 nm bulk CMOS process. The proposed Doherty PA exhibits 27.2 dBm saturated output power with 24.5% power-added efficiency (PAE) at 5.8 GHz. The measured error vector magnitude with 40/80 MHz of 64-QAM/256-QAM is 2.5%/1.8% with 20.7/17 dBm average output power, 9.5%/5.3% average PAE, and −33.2/−36.3 dBc adjacent channel leakage ratio without any DPD.

A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM–PM Distortion Self-Compensation

This paper presents a fully integrated wideband current-mode digital polar power amplifier (DPA) in CMOS with built-in AM–PM distortion self-compensation. Feedforward capacitors are implemented in each differential cascode digital power cell. These feedforward capacitors operate together with a proposed DPA biasing scheme to minimize the DPA output device capacitance $C_{d}$ variations over a wide output power range and a wide carrier frequency bandwidth, resulting in DPA AM–PM distortion reduction. A three-coil transformer-based DPA output passive network is implemented within a single transformer footprint (330 $\mu \text{m} \,\, \times $ 330 $\mu \text{m}$ ) and provides parallel power combining and load impedance transformation with a low loss, an octave bandwidth, and a large impedance transformation ratio. Moreover, this proposed power amplifier (PA) output passive network shows a desensitized phase response to $C_{d}$ variations and further suppresses the DPA AM–PM distortion. Both proposed AM–PM distortion self-compensation techniques are effective for a large carrier frequency range and a wide modulation bandwidth, and are independent of the DPA AM control codes. This results in a superior inherent DPA phase linearity and reduces or even eliminates the need for phase pre-distortion, which dramatically simplifies the DPA pre-distortion computations. As a proof-of-concept, a 2–4.3 GHz wideband DPA is implemented in a standard 28-nm bulk CMOS process. Operating with a low supply voltage of 1.4 V for enhanced reliability, the DPA demonstrates ±0.5 dB PA output power bandwidth from 2 to 4.3 GHz with +24.9 dBm peak output power at 3.1 GHz. The measured peak PA drain efficiency is 42.7% at 2.5 GHz and is more than 27% from 2 to 4.3 GHz. The measured PA AM–PM distortion is within 6.8° at 2.8 GHz over the PA output power dynamic range of 25 dB, achieving the lowest AM–PM distortion among recently reported current-mode DPAs in the same frequency range. Without any phase pre-distortion, modulation measurements with a 20-MHz 802.11n standard compliant signal demonstrate 2.95% rms error vector magnitude, −33.5 dBc adjacent channel leakage ratio, 15.6% PA drain efficiency, and +14.6 dBm PA average output power at 2.8 GHz.

0.4–3.0 GHz highly efficient harmonic‐tuned power amplifier

An optimisation-based method is proposed for the design of highly efficient harmonic tuned-power amplifier (HT-PA) with multi-octave bandwidth. The distributed basic matching cell with L-type structure is utilised to construct the broadband matching network, whose topology and parameters are determined through optimisation. To validate the proposed method, a 0.4–3.0 GHz HT-PA is implemented and the power added efficiency of 53–72%, output power of more than 40 dBm and 10–12 dB gain are achieved across the frequency band. When tested with 20 MHz long-term-evolution advanced signals, the broadband HT-PA shows about –30 dBc adjacent channel leakage ratio at about 36 dBm average output power, with drain efficiency higher than 36%.

Multi-mode multi-band power amplifier module with high low-power efficiency**Project supported by the National Natural Science Foundation of China (No. 61201244).

Increasingly, mobile communications standards require high power efficiency and low currents in the low power mode. This paper proposes a fully-integrated multi-mode and multi-band power amplifier module (PAM) to meet these requirements. A dual-path PAM is designed for high-power mode (HPM), medium-power mode (MPM), and low-power mode (LPM) operations without any series switches for different mode selection. Good performance and significant current saving can be achieved by using an optimized load impedance design for each power mode. The PAM is tapeout with the InGaP/GaAs heterojunction bipolar transistor (HBT) process and the 0.18-μm complementary metal-oxide semiconductor (CMOS) process. The test results show that the PAM achieves a very low quiescent current of 3 mA in LPM. Meanwhile, across the 1.7–2.0 GHz frequency, the PAM performs well. In HPM, the output power is 28 dBm with at least 39.4% PAE and −40 dBc adjacent channel leakage ratio 1 (ACLR1). In MPM, the output power is 17 dBm, with at least 21.3% PAE and −43 dBc ACLR1. In LPM, the output power is 8 dBm, with at least 18.2% PAE and −40 dBc ACLR1.

High Efficiency WCDMA Power Amplifier With Pulsed Load Modulation (PLM)

Complex non-constant-envelope modulations are often used in wireless communications. A power amplifier (PA) is developed based on the concept of pulsed load modulation (PLM) that can enhance the power efficiency of the PA when the output power is back off from the peak due to modulations. The PLM technique utilizes the time-varying behavior of switched resonators to form an optimal, power dependent load impedance. The switched resonator consists of a balanced pair of switching mode PAs that drive a high-Q bandpass filter. In addition to its efficiency enhancement through PLM, the PA is able to preserve the linearity of complex modulations through the architecture of envelope delta-sigma modulation (EDSM). In this paper, a 1.87 GHz PLM power amplifier is fabricated with a pair of 0.35 μm GaAs pHEMT devices. The duty cycle tests show its significant improvement on power efficiency at different back-off levels over traditional Class-B amplifiers. The PA module is also tested with a single-channel WCDMA signal with peak to average ratio (PAR) of 10.8 dB. It has achieved 39 dBc adjacent channel leakage ratio (ACLR) at 5 MHz offsets without needing additional linearization techniques. The power added efficiency in this case is 43% including the loss of the output filter and 52.6% if the loss of the filter is de-embedded.

분산 소자 형태의 마이너스 군지연 회로를 이용한 고효율 피드포워드 증폭기의 분석 및 설계

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

Linearity optimization of a high power Doherty amplifier based on post-distortion compensation

The linearity of a 30-W high-power Doherty amplifier is optimized using post-distortion compensation. A balanced high-power Doherty amplifier using two push-pull laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) is linearized by optimum adjustment of the peaking compensation line, shunt capacitors, and gate biases. The measured results of an optimized Doherty amplifier for a four-carrier wideband code division multiple access (W-CDMA) signal, achieved -43 dBc adjacent channel leakage ratio (ACLR) at a /spl plusmn/5 MHz offset frequency. This is an ACLR improvement of 12.2dB and 6.5dB in comparison to the Doherty amplifier before optimization and a ClassAB amplifier, respectively.

A microwave Doherty amplifier employing envelope tracking technique for high efficiency and linearity

In this letter, we demonstrate a microwave Doherty amplifier employing an input signal envelope tracking technique. In the amplifier, the gate bias of the peaking amplifier is controlled according to the magnitude of the envelope. A 2.14-GHz Doherty amplifier is implemented using 4-W PEP LDMOSFETs, and an adaptive controlled gate bias circuit is constructed and the control shape is optimized experimentally. The performance of the microwave Doherty amplifier is compared with that of a class AB amplifier using one-tone, two-tone, and forward-link wideband code-division multiple access (WCDMA) signals. For a forward-link WCDMA signal, the measured power added efficiency (PAE) of the microwave Doherty amplifier is 39.4% at -30 dBc adjacent channel leakage ratio (ACLR), while that of the comparable class AB amplifier is 24.2% at the same ACLR level.