dB Spurious Free Dynamic Range Research Articles

A Fast and Cost-Effective Calibration Strategy of Inter-Stage Residual Amplification Errors for Cyclic-Pipelined ADCs

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm2.

A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis

This study proposes a novel 6-transistor bootstrapped switch with minimized sampling and holding error obtained through sampling window error analysis for SAR ADC design. The proposed switch design strategically mitigates channel charge injection and minimizes the input signal dependency of on-resistance by optimizing its sizing parameters. To counteract channel charge effects, dummy NMOS and PMOS components are judiciously employed, culminating in a substantial improvement in the effective number of bits (ENOB). The complete analysis of the proposed circuit is done using the Cadence Virtuoso SCL 0.18[Formula: see text][Formula: see text]m CMOS process. For a 51.514[Formula: see text]kHz sinusoidal 1[Formula: see text]V peak-to-peak differential input signal with a 1[Formula: see text]MSPs clock speed, the proposed circuit achieves 2.0141[Formula: see text]mV maximum sampling window error, 0.131[Formula: see text][Formula: see text]W power consumption, 84.67 dB signal-to-noise ratio (SNR), 84.67 signal-to-noise and distortion (SINAD) ratio and 86.02 dB spurious-free dynamic range (SFDR), which produces 13.77 bits ENOB. For the impacts of process variations and mismatch on switch performance, a comprehensive 500-point Monte Carlo (MC) simulation of the proposed bootstrap switch is conducted in this study. Post-layout results show that the proposed circuit is suitable for IoT applications.

A 102.1-dB SNDR oversampling merge-mismatch-error-shaping SAR ADC in 180 nm CMOS

In this paper, we propose a merge-mismatch-error-shaping (M-MES) noise shaping SAR ADC as a solution to address the limitation of SNDR caused by the non-linearity resulting from DAC mismatch. The proposed M-MES technique is based on MES with the introduction of capacitive merging to mitigate the degradation of dynamic range (DR) in ADCs. In addition, to meet the high signal-to-noise ratio (SNR) and low power requirements of the ADC, cascaded integrator feed-forward (CIFF) noise shaping ADC in this paper is a first-order filter based on a closed-loop amplifier. The proposed ADC was simulated and designed in a 180-nm CMOS process, which consumes 449 μW of power when operating at 1 MS/s sampling frequency. According to the post-simulation results, under a 3.3-V supply and at an oversampling ratio (OSR) of 500, the proposed ADC achieves Schreier FoMS of 168.5 dB with 102.1 dB signal to noise and distortion ratio (SNDR) and 102.2 dB spurious free dynamic range (SFDR).

A 14-bit 1-GS/s Pipelined-SAR ADC in 28-nm CMOS with Foreground and Background Calibration

A 14-bit 1-GS/s Pipelined-Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in 28-nm CMOS is presented in this paper. In the initial phase, a pair of SAR ADCs employing the Time-Interleaved (TI) technique are employed to attain the necessary sampling rate. A multi-comparators structure is used to increase the speed and improve the mismatch. We have implemented a foreground calibration technique to address capacitor mismatch, optimizing its processing logic to enhance the chip’s speed. The interstage operational amplifier adopts a two-stage structure. Some structural changes are presented to optimize its bandwidth and phase margin. A background calibration method for gain error is implemented. In the subsequent phase, we employ four SAR ADCs utilizing the TI method. The outcomes demonstrate that the ADC delivers a Signal-to-Noise and Distortion Ratio (SNDR) of 65.58 dB and a Spurious-Free Dynamic Range (SFDR) of 72.12 dB at a 1-GS/s sampling rate without calibration, and 69.02 dB SNDR and 81.26 dB SFDR at the same 1-GS/s sampling rate with calibration. The core layout occupies an area of 0.6 mm2 and consumes 225.02 mW of power.

Design of High-Speed SAR ADC based on 40nm CMOS Process

In this paper, a high-speed successive approximation analog-to-digital converter is designed based on a 40 nm CMOS process. A split-capacitor Vcm-Based switching strategy is designed, which is able to keep the output common-mode voltage constant for the DAC capacitor array without using Vcm level drive, while saving half of the capacitance compared to the conventional switching strategy and greatly reducing the area consumption. It also combines the features of binary redundancy technology and non-binary redundancy technology by splitting the highest bit capacitor to the lower bit, which enables the DAC array to generate two additional redundant bits without adding other capacitors, reducing its requirements for noise and establishment accuracy; and it adopts asynchronous timing control without external clocks, which is conducive to improving the speed of SAR ADCs and reducing the design complexity. The designed SAR ADC achieves 9.83 bit effective bits, 60.9 dB signal-to-noise distortion ratio, 77.2 dB spurious-free dynamic range, 1.68 mW overall power consumption, and 18.46 fJ/conv-step superiority at a supply voltage of 1.1 V and a sampling frequency of 100 MHz through simulation.

A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

This article presents a 16-bit 2.5-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with on-chip foreground calibration, including two digital-to-analog converters (DACs). Apart from the traditional segmented capacitor DAC (CDAC) used in ADC, the assistant DAC (ADAC) is added to store errors, including offset and mismatch, and compensate them based on the calculation. The high-performance comparator and modified timings are used to meet the needs for speed and resolution while paralleling switches are applied to reduce the impacts of charge injection. The proposed SAR ADC has been designed and fabricated in a 55 nm CMOS process with an area of 0.76 mm2. The 81.51 dB signal to noise-plus-distortion ratio (SNDR) and the 96.8 dB spurious-free dynamic range (SFDR) are measured at 2.5 MS/s respectively, while the integral nonlinearity (INL) is ＋2.4/−1.7 LSB. The core ADC consumes 25.8 mW power under 3.3 V analog supply and 1.2 V digital supply with the Schreier figure-of-merit (FOMs) 159.8 dB.

SAR ADC for a Multimode Radar Transceiver with Offset Calibration

In this paper, we design a successive approximation register (SAR) analog-to-digital converter (ADC) suitable for multimode radar transceivers. For multimode radars, the sampling rate required by ADC varies according to the continuous wave (CW) or frequency modulated continuous wave (FMCW) used for operation. Therefore, depending on which waveform is used, the input is designed to enter two paths. For path 1, we obtained 9.23 bits of effective number of bits (ENOB), 57.35 dB of signal-to-noise distortion ratio (SNDR), and 64.62 dB of spurious free dynamic range (SFDR), and the power consumption was 0.3481 mW, resulting in a figure of merit (FOM) of 28.9 fJ/Conv-Step. On path 2, we obtained an 8.97 bit of ENOB, 55.76 dB of SNDR, and 60.53 dB of SFDR, and the power consumption was 1.72 μW, resulting in a FOM of 34.2 fJ/Conv-Step. Further, a circuit was constructed to reduce the offset of the comparator. As a result of 100 Monte Carlo simulations, the offset was reduced from -46 mV/+50 mV to -4 mV/+4 mV when the worst case was considered.

A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes

This paper presents a 16-bit successive approximation register analog-to-digital converter (ADC) achieving over-100 dB spurious-free dynamic range (SFDR). This ADC uses V_CM-based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a <i>level-2</i> capacitor swapping scheme is proposed to achieve superior DAC linearity by using two intrinsic true random number sequences. A prototype ADC is fabricated in 180 nm CMOS technology and occupies an active area of 0.53 mm². At 1 MS/s, it consumes a total power of 1.05 mW from a supply of 1.8 V. The measured differential and integral nonlinearity are &#x2212;0.65/&#x002B;0.45 and &#x2212;2.2/&#x002B;2.1 least significant bit. With an input of 1 kHz, the measured SNDR and SFDR are 83 dB and 100 dB. The effective number of bits is 13.5, which is equivalent to a Schreier figure-of-merit of 169.8 dB.

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

TI-ADC multi-channel mismatch estimation and calibration in ultra-high-speed optical signal acquisition system.

This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implemented in 28 nm CMOS, reaches a 41 dB SFDR with an input signal of 1.2 GHz and 5 dBm after the proposed background offset and gain mismatch calibration. Compared with previous works, the spurious-free dynamic range (SFDR) and the effective number of bits (ENOB) are better, the estimation accuracy is higher, the error is smaller and the faster speed of convergence improves the efficiency of signal processing.

A Symmetric Group Control Dynamic Element Matching Method Applied in High Resolution SAR ADCs for Biomedical Applications

Capacitor mismatch plays an important part in the spurious-free dynamic range (SFDR) performance of high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). This paper presents a symmetric group control dynamic element matching (SGCDEM) method aiming at enhancing SFDR of SAR ADCs applied in biomedical applications. The proposed scheme symmetrically divides the capacitor array into four sub-DACs, using quantization results corresponding to each sub-DAC as rotary control codes to symmetrically control the rotation of the capacitors. In order to improve the energy efficiency and save chip area, the proposed method replaces the pseudo-random number generator (PRNG) with quantization results of ADC as the rotary control code. Moreover, split rotator technology is applied in the proposed scheme to reduce the number of multiplexers (MUX) used in the rotator, which introduces a low logic depth. The proposed architecture has been implemented on a 12-bit SAR ADC model in MATLAB in order to verify its performances. After taking a standard deviation of 1% for the unit capacitance into consideration, this method achieves above 77.3[Formula: see text]dB SFDR, enabling to correct the SFDR by more than 23.6[Formula: see text]dB compared with the structure without DEM.

A second-order noise-shaping SAR ADC with error-feedback structure and data weighted averaging

This paper presents a second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing the error-feedback (EF) structure. With the finite impulse response (FIR) filter based on a single operational transconductance amplifier (OTA), it realizes noise transfer function (NTF) zeros optimization. The specifications of OTA are relaxed without high-gain and fast-settling. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-coded 4-bit MSBs are implemented with the data weighted averaging (DWA) technique. The overall architecture is simple and robust. It does not need additional complicated digital calibrations, and only requires minor modifications to the standard SAR ADC. Design and simulation in a 130 ​nm CMOS process, the prototype consumes 96 ​μW of power when operating at 1 ​MS/s sampling frequency. The proposed ADC achieves peak Schreier FoM of 165 ​dB with 76.95 ​dB signal to noise and distortion ratio (SNDR) and 97.34 ​dB spurious free dynamic range (SFDR) at an oversampling ratio (OSR) of 8.

Suppression of third-order intermodulation distortion in analog photonic link based on an integrated polarization division multiplexing Mach–Zehnder modulator

A simple and linear analog photonic link (APL) based on a single integrated polarization division multiplexing Mach–Zehnder modulator (PDM-MZM) is proposed with suppressed third-order intermodulation distortion (IMD3). By properly selecting the modulation indexes of radio frequency (RF) signals and bias angles in the two sub-modulators, the electric/optical power ratio is changed and thus two nonlinear distortion signals with opposite phases are constructed to cancel out IMD3 of the link. Therefore, the IMD3 can be suppressed and the spurious-free dynamic range (SFDR) of the system can be improved. Only one electrode in each sub-modulator is used in the experiment. Experimental results show that compared with the conventional link based on a single MZM, 33.7-dB reduction of IMD3 is achieved and an enhancement of 17.6 dB in SFDR can be obtained. Besides, the proposed APL is test by a 16 quadrature amplitude modulation (QAM) RF signal and the error vector magnitude (EVM) and adjacent channel power ratio (ACPR) of the link are measured.

An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method

ABSTRACT An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method is presented for Nyquist-rate Digital to Analog converters (DACs). In contrast to the RSTC DEM method, the presented method prevents the Spurious-free dynamic range (SFDR) reduction in DACs in low signal frequencies. Also, while ”RSTC with the restricted jumping technique” method is unable to prevent the SFDR reduction in low frequencies for non-full-scale sinusoidal signals, this new method prevents the SFDR reduction in low frequencies for both full-scale and non-full-scale sinusoidal signals. The Fast fourier transform (FFT) analysis for a behavioural model of a 6-Bit thermometer coded DAC at ( is the signal frequency and is the sample rate) shows 2.1 dB SFDR improvement in comparison to ”RSTC with the restricted jumping technique” method. In addition, the presented method achieves a reasonable trade-off between SFDR and Switching activity in comparison to other DEM methods.

An analog photonic down-conversion link with simultaneous IMD3 distortion suppression and dispersion-induced power fading compensation

A novel analog photonic down-conversion link based on a polarization modulator and a phase modulator with simultaneous linear optimization and chromatic dispersion-induced power fading compensation is proposed and experimentally demonstrated. By introducing an appropriate phase shift to the optical sidebands, chromatic dispersion-induced power fading is compensated, and third-order intermodulation distortion terms are eliminated in the same time. The scheme exhibits wide operating frequency range due to its no use of filters and frequency-dependent electrical or optical devices. The scheme is robust, as the operation of the polarization modulator and the phase modulator are independent of signal amplitude and bias voltage. Experimental results show that, for a 25-km transmission link, an improvement of more than 15.5 dB in spurious-free dynamic range is achieved and the dispersion-induced power fading is compensated at the same time. In addition, benefiting from the power compensation and significant suppression of IMD3, a 16QAM vector signal is demonstrated to have a good demodulation performance.

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

A pipeline analog-to-digital converter (ADC) with high power efficiency is implemented in this paper. The ADC architecture consists of 3.5b, 3.5b, 3.5b, and 4b sub-ADCs. For the first three stages, a current-reuse technique is employed in the current mode multiplying digital-to-analog converters (MDACs). An operational transconductance amplifier (OTA) converts an input voltage into current; A current-steering DAC reuses the OTA bias current. The OTA and the DAC generate the sub-ADC residue in a current domain. As a result, both power consumption and thermal noise for the MDAC are reduced. A transimpedance amplifier (TIA) with a feedback resistor is utilized to convert the current signal to a voltage residue signal for the next stage. An off-chip calibration scheme is used to correct interstage gain and nonlinearity errors. The fabricated ADC achieves 68.1 dB signal-to-noise-and-distortion ratio (SNDR) and 82.3 dB spurious free dynamic range (SFDR) for a sinusoidal input at 4.17 MHz. The ADC operates at a maximum sampling frequency of 260 MHz. With an input signal at 123.129 MHz, the measured SNDR/SFDR are 66.3/78.22 dB, respectively. The total power consumption for the ADC running at maximum speed is 15.38 mW. Thus, the pipeline ADC achieves a 167.4 dB figure-of-merit (FoM). The chip was manufactured in a TSMC 40-nm CMOS process.

Wideband OPLL photonic integrated circuit enabling ultrahigh dynamic range PM RF/photonic link

The RF/photonic link is the basic element of microwave photonics. Previous RF photonic links often rely on optical intensity modulation. The inherent modulation nonlinearity leads to inadequate spurious free dynamic range (SFDR) for many sought-after microwave photonic applications in radar. A new phase-modulated (PM) link with an optical phase-locked loop (OPLL) demodulator could afford a promising solution for the SFDR. However, the efficacy of the PM link approach remained unsubstantiated as previous OPLL implementations had too restricted of a bandwidth for realistic applications. Here, we present a new OPLL photonic integrated circuit (PIC) chip that offered quadrupled bandwidth enhancement over the state of the art. The OPLL PIC represents the first OPLL linear optical phase demodulator with sufficient bandwidth for realistic microwave photonic applications. With help of the OPLL PIC, a PM RF/photonic link demonstrated a record-breaking SFDR of ∼129.3 dB·Hz2/3 and a 3 dB SFDR bandwidth of ∼1 GHz. The combined SFDR and bandwidth performance amounts to around 1 order of magnitude improvement over the prior state of the art.

A fully CMOS RF down-converter with 81.88 dB SFDR for IEEE 802.15.4 based wireless systems

In this paper, the challenges of dense integration, low power, low-cost, low-noise and high spurious free dynamic range (SFDR) required by the RF front-end (RFE) circuits for low-rate wireless personal area networks are addressed. The proposed RF down-converter circuit utilizes a low-noise transconductance amplifier stage to improve the noise performance of the highly noisy switching stage of the down-converter. The nonlinearity of the low-noise stage is compensated by employing post-distortion based harmonic cancellation for dynamic range improvement of the RF front-end circuit. The proposed RFE is designed and realised in UMC 180 nm CMOS process technology. The post-layout characterization of the circuit shows an third-order intercept point with reference to the input (IIP3) of 11.83 dBm, double-sideband noise figure of 5.9 dB, conversion gain of 17.87 dB and offers a SFDR of 81.88 dB while consuming 5 mA current from 1.8 V. The proposed circuit consumes an area of 0.1 mm2. The proposed RF down-converter boasts a 17 dB improvement in SFDR over the recently proposed RFE in the literature. The proposed RFE is also correlated with the other existing state-of-art RFE circuits recorded in the literature for Zigbee applications.

Photonic down‐conversion and linearisation with tunable IF bandwidth and improved spurious‐free dynamic range

A scheme for simultaneous down-conversion and linearisation of radio-frequency (RF) signals is proposed and demonstrated. Based on carrier-suppressed double-sideband modulation, the input RF signal can be down-converted to any intermediate frequency (IF) tone in the range of 8–12 GHz. Compared with the down-conversion scheme with two cascaded intensity modulators, the proposed scheme has improvement of >21 dB of the suppression ratio of third-order intermodulation distortion and 6.17 dB of spurious-free dynamic range.

A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current

Pipeline analog-to-digital converters (ADCs), which dominated high-speed and high-resolution applications, suffered from weak improvement in power efficiency. To address such a problem, this brief presents a 14-bit split-pipeline opamp-sharing ADC, with background calibration that optimizes duty-cycle ratio and amplifier power consumption in the shared opamp. Based on the interstage gain (that includes settling) error estimated by the split ADC calibration engine, the clock duty-cycle ratio and the bias current are adjusted to achieve better dynamic settling and resolution trade-offs. Operating at 100 MS/s with a 9-MHz input signal, the ADC achieves 46.5 dB of signal-to-noise-and-distortion ratio (SNDR) and 59.6 dB of spurious-free dynamic range (SFDR) before calibration, and after calibration, it improves to 71.7 dB of SNDR and 84.4 dB of SFDR, respectively. The ADC maintains an SNDR over 68.5 dB within the full Nyquist bandwidth consuming 32 mW of power, which yields a Walden figure-of-merit (FoM) of 147.2 fJ/conversion-step and a Schreier FoM of 160.4 dB.