A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes

Abstract

This paper presents a 16-bit successive approximation register analog-to-digital converter (ADC) achieving over-100 dB spurious-free dynamic range (SFDR). This ADC uses V_CM-based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a <i>level-2</i> capacitor swapping scheme is proposed to achieve superior DAC linearity by using two intrinsic true random number sequences. A prototype ADC is fabricated in 180 nm CMOS technology and occupies an active area of 0.53 mm². At 1 MS/s, it consumes a total power of 1.05 mW from a supply of 1.8 V. The measured differential and integral nonlinearity are &#x2212;0.65/&#x002B;0.45 and &#x2212;2.2/&#x002B;2.1 least significant bit. With an input of 1 kHz, the measured SNDR and SFDR are 83 dB and 100 dB. The effective number of bits is 13.5, which is equivalent to a Schreier figure-of-merit of 169.8 dB.