dB SINAD Research Articles

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

ABSTRACTThis article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m2.

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

The Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6dB and a SINAD of 55dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC׳s 0.35μm high-voltage process. The use of overlapping subranges reduced the DNL error from +5.14/−1 LSB to +1.27/−0.92 LSB, and improved the INL error from +5.35/−5.34 LSB to +3.17/−3.18 LSB. At a sampling rate of 1.1MS/s the ADC achieved 41.5dB SFDR, 34.2dB SINAD, and consumed 242μW/channel dynamic power. An individual ADC channel is only 22μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.

Design of a 12-bit 1 MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging system

A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35um 2P4M CMOS process. At a 3.3/5V power supply, the proposed SAR-ADC achieves 67.64dB SINAD at 1MS/s, consumes 10mW power and occupies a core area of 1180×1080um2.

Low power HFET down converter MMIC's for wireless communication applications

An ultra low power GaAs HFET (heterojunction FET) amplifier/mixer MMIC was designed and characterized for portable communication applications in the 900 MHz band. A completely monolithic LNA (80 mil/spl times/42 mil) achieved 10 dB gain, 2.5 dB NF and -4 dBm input IP3 at an operating current of 0.5 mA @ 1.0 V. Receiver sensitivity of a front-end circuit consisting of the LNA and a dual gate FET mixer was characterized using the 12 dB SINAD method. The IC achieved -117 dBm receiver sensitivity in the 900 MHz cellular band. The total power consumption of this miniature down converter was about 2 mW. The HFET down converter IC achieved the same receiver sensitivity as a MESFET down converter at 1/5th of the power. The extremely low power dissipation, high third order intercept point, high level of integration, and very good RF performance of this monolithic IC make it an ideal candidate for wireless applications.

Large-scale integration in systems design—Bipolar technology : W. E. Wicks, Electro-Technol.84, No. 4, October (1969), p. 61

A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35 um 2P4M CMOS process. At a 3.3/5 V power supply, the proposed SAR-ADC achieves 67.64 dB SINAD at 1MS/s, consumes 10 mW power and occupies a core area of 1180×1080 um2.