dB Back-off Power Research Articles

Implementation of Flat Gain Broadband Power Amplifier With Impedance Rotation Compensation

The conventional broadband impedance matching network in low-pass structure cannot present adequate broadband impedance rotation for the optimum broadband operation of the power amplifier (PA), resulting in performance variations and degradations. The underlying constraint is the phenomenon of opposite impedance rotation. Against such a backdrop, this paper presents a methodology using the band-pass topology to compensate the frequency-variable response of the PA. The CGH40010F from Cree is used to verify the effectiveness of this compensation method. The experimental results are in good agreement with the simulation. The proposed PA yields good gain flatness (±0.5 dB), input/output return loss (>13 dB), and high power added efficiency (>60 %) over the band from 1.7 to 2.7 GHz. After digital predistortion, the measured adjacent channel power ratio is about −55 and −50 dBc at ±5 and ±10 MHz offset when the PA is driven by 5- and 10-MHz WCDMA signals at 6.5 ~ 7 dB power back-off.

X‐band two‐stage Doherty power amplifier based on pre‐matched GaN‐HEMTs

This study presents an X-band two-stage Doherty power amplifier (DPA) using pre-matched gallium-nitride high electron mobility transistors (GaN-HEMTs). The pre-matched GaN-HEMT includes partial matching circuits in the package using bond-wires and capacitors. To obtain broad bandwidth and low loss, the pre-matching circuits were carefully designed to have a low matching quality factor. The optimum second harmonic impedance, which was extracted from the harmonic source/load pull simulations, was applied to the pre-matching circuits for high efficiency. Using the pre-matched GaN-HEMTs, an X-band two-stage power amplifier (PA) was designed and implemented. By combining two two-stage PAs in parallel, a DPA was built. The implemented DPA exhibited a max gain of 25.5 dB and an output power from 42.5 to 45.8 dBm at the frequency band from 7.9 to 8.4 GHz. It also showed a high efficiency of 37.8% at the 6 dB back-off output power level of 39.6 dBm.

A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS

A CMOS class-E outphasing RF power amplifier is presented with a new passive combining circuit that provides high efficiency and high output power. An efficiency enhancement circuit and a power enhancement circuit are proposed as part of the combiner that improve efficiency at power back-off and increase output power without violating reliability limits, respectively. The proposed power amplifier is designed in a 45nm CMOS technology. The power amplifier (PA) delivers 29.5 dBm peak output power at 2.4 GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off, and 21.16% drain efficiency at 6 dB power back-off. The proposed power amplifier shows excellent linearity with digital pre-distortion. Better than -50 dBc adjacent channel power ratio (ACPR) is obtained with 64-QAM long-term evolution (LTE) signal with 10 MHz and 20 MHz bandwidth. For two-carrier 20 MHz LTE signal, -44 dBc ACPR is achieved. 21% average drain efficiency is obtained with LTE signal with a 6 dB peak-to-average power ratio. The PA is also tested with 802.11g WLAN signal and it satisfies the spectral mask requirement with high margin. 1.4% (-37.1 dB) error vector magnitude (EVM) is obtained with LTE signal (64-QAM) with a 10 MHz bandwidth.

A Broadband Doherty Power Amplifier Based on Continuous-Mode Technology

In this paper, a novel broadband Doherty power amplifier based on the continuous-mode technique (C-DPA) is proposed. The amplifier is focused on manipulating harmonic components in a Doherty power amplifier (DPA) structure to achieve improved bandwidth and efficiency. In a conventional DPA, harmonic isolation is typically required between the two transistors to prevent them from modulating each other at harmonic frequencies. However, as presented in this paper, such isolation is not actually necessary. On the contrary, by allowing the two transistors to modulate each other at harmonic frequencies with the help of a properly designed postharmonic tuning network, a series of highly efficient DPA modes can be created over a continuous frequency band, leading to a broadband C-DPA. Based on the proposed method, an example of a C-DPA working from 1.65 to 2.75 GHz was designed. According to the measured results, the designed C-DPA exhibits a 52%–66% efficiency at a −6 dB power backoff and a power utilization factor higher than 1.08 over the 1.1-GHz band. In addition, when simulated by a 7.5-dB peak-to-average power ratio 20-MHz LTE signal, the example C-DPA exhibits an efficiency of 46%–62% while maintaining an adjacent channel power ratio below −45 dBc after linearization over the full 1.1-GHz band. To the best of our knowledge, this is the first proposed C-DPA and a state-of-the-art performance for broadband DPAs.

Improved Doherty Amplifier Design with Minimum Phase Delay in Output Matching Network for Wideband Application

This letter presents an improved Doherty power amplifier (DPA) for high-efficiency and wideband operations. To achieve the impedance transformations both in the low power region and at saturation, a design approach is proposed to determine the desired minimum phase delays of the carrier and peaking output matching networks, which can simplify the load modulation network of the DPA and extend the bandwidth. For verification, a 1.6-2.2 GHz asymmetric DPA was designed and measured. The designed DPA can deliver an efficiency of 51%-55% at 10 dB back-off power over the whole band. For a 20 MHz LTE signal, an average efficiency of higher than 50% can be achieved at 36 dBm average output power with the linearity of -48 dBc after linearization across the band.

Ka‐band doherty power amplifier with 26.9 dBm output power, 42% peak PAE and 32% back‐off PAE using GaAs PHEMTS

The authors present the design and development of a two stage Doherty power amplifier (DPA) in the Ka-band. The amplifier is fabricated in a 0.15-μm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process. The DPA has a centre frequency of 26.6 GHz, a measured small signal gain of 10.5 dB, output power at 1-dB compression point (P1 dB) of 26.9 dBm, maximum power added efficiency (PAE) of 42%, and PAE of 32% at 6 dB back-off power. To the best of the author's knowledge, this DPA is the first millimetre-wave (mm-wave) power amplifier to achieve a record 32% PAE at 6-dB back-off power from 26.9 dBm at Ka-band.

2.6 GHz GaN-HEMT Power Amplifier MMIC for LTE Small-Cell Applications

This paper presents a two-stage power amplifier MMIC using a 0.4 μm GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of 2.0×1.9 mm² and was mounted on a 4×4 QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.

A Bandwidth Enhanced Doherty Power Amplifier With a Compact Output Combiner

This letter introduces a broadband and compact output combiner for Doherty power amplifier (DPA). A grounded quarter Wavelength $(\lambda/4)$ line is added to the output of the peaking amplifier, which helps to compensate for the bandwidth limiting effect that happens in the conventional combiner. Frequency response analysis indicates that stable impedance is achieved across a wide band for the carrier PA. For demonstration, a DPA prototype based on the proposed structure is implemented using two 10 W GaN HEMT transistors. At 6 dB back-off power, over 42% drain efficiency is obtained from 1.5 GHz to 2.5 GHz, accounting for 50% fractional bandwidth. In addition, a minimum of 55% drain efficiency is maintained at saturation in the same frequency band.

A Broadband Mixed-Signal CMOS Power Amplifier With a Hybrid Class-G Doherty Efficiency Enhancement Technique

This paper presents a broadband mixed-signal CMOS power amplifier (PA) with a hybrid Class-G Doherty architecture for PA efficiency enhancement up to the deep power back-off (PBO) region. Our proposed mixed-signal linearization technique ensures the PA’s amplitude modulation (AM)–AM linearity by digital PA operation and suppresses the PA’s AM–phase modulation (PM) nonlinearity by real-time analog phase compensation. The PA is fully integrated in a standard 65 nm bulk CMOS process, and achieves a peak output power ( ${P_{{\text{out}}}}$ ) of $+ {{26}}.{{7}}\;{\text{dBm}}$ with a 40.2% peak drain efficiency (DE) at 3.71 GHz. The DE at 6 and 12 dB PBO is $1.8\times$ and $2.6 \times$ over the reference Class-B PA operation, advancing the state-of-the-art CMOS PA PBO efficiency performance. The PA 1 dB bandwidth is extended from 1.08 to 1.8 GHz by reconfiguring the phase difference between the main and auxiliary paths in the Doherty PA. In the modulation measurements with 1 MSym/s 16 QAM signals, the PA performs dynamic hybrid Class-G Doherty operation and achieves $+ {{20}}.{{8}}\;{\text{dBm}}$ peak ${P_{{\text{out}}}}$ with 28.8% DE at 3.71 GHz and $2.42\times$ efficiency enhancement at 8.1 dB PBO over Class-B operation. The real-time AM–PM linearization technique achieves 3.3 and 2.9 dB improvements on the EVM and adjacent channel leakage ratio (ACLR), respectively. The broadband Class-G Doherty operation is also demonstrated with modulated signals.

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

A fully-integrated reconfigurable dual-band (760–960 MHz and 2.4–2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by ×3.24 and ×1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by ×2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.

Gate Bias Adaptation of Doherty Power Amplifier for High Efficiency and High Power

This letter presents an approach to maximize the output power and efficiency of a Doherty power amplifier (PA). The conventional carrier PA having 2R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OPT</sub> match, used in a symmetric Doherty PA, does not deliver the saturated high efficiency at the 6 dB back-off power but at the 5.5 dB back-off power due to the knee voltage effect. To solve the problem, the gate biases of the carrier and peaking PAs are adapted. The gate bias voltage of the carrier PA is optimized for a higher peak output power, delivering a 3 dB larger peak power at R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OPT</sub> match. That of the peaking PA is also optimized to have the same peak power of the carrier PA. A Doherty PA with the concept is designed using a 45 W gallium nitride (GaN) high electron mobility transistors (HEMT) for the carrier and peaking cells at 1.94 GHz. The measured average output power, drain/power-added efficiencies and gain are 44.35 dBm, 60.5/57.2%, and 12.75 dB for a 10 MHz long term evolution (LTE) signal with a 6.5 dB peak-to-average power ratio (PAPR).

A Wideband Distributed Amplifier Employing an Envelope Tracking Technique

This letter presents a wideband distributed amplifier employing an envelope tracking (ET) technique for high efficiency and linearity. By applying the ET technique to the distributed amplifier after linearity optimization, the distributed amplifier's defects such as low output power and low efficiency can be overcome and high efficiency and linearity can be achieved. For verification, the distributed amplifier is designed using two Nitronex NPTB00025 GaN HEMT devices and tested with LTE signals at 2.6 GHz. From the tested results at an average output power of 37 dBm (10 dB back-off power), the proposed circuit shows an adjacent channel leakage ratio (ACLR) below -45 dBc at ±5 MHz offset, with a gain over 14.1 dB and a power-added efficiency (PAE) over 21.9% over a 300 MHz bandwidth.

Reconfigurable Doherty Power Amplifier for Multifrequency Wireless Radio Systems

This paper proposes a frequency-agile Doherty amplifier capable of efficiently amplifying multiband wireless signals located at widely spaced frequencies. Starting with the study of the load modulation concept in the Doherty technique and the various frequency-dependent components involved in its realization, this paper suggests a simplified and effective design methodology for the development of frequency-agile and reconfigurable Doherty amplifiers using a small number of electronically tunable devices. As a proof of concept, a reconfigurable Doherty power amplifier (PA) prototype is designed and fabricated to operate at 1.9, 2.14, and 2.6 GHz. The measurement results obtained using a continuous-wave signal revealed drain efficiencies of approximately 70% and 60% at the peak power and 6 dB back-off power, respectively, for the three targeted operating frequencies. In addition, the reconfigurable Doherty amplifier was successfully linearized when driven with 20-MHz wavelength code-division multiple access and longterm evolution signals, using a Volterra-based digital predistrtion algorithm which exploits a pruned Volterra series.

High-efficiency inverse class-E power amplifier with envelope tracking technique

This letter describes a highly efficient inverse class-E power amplifier (PA) with an envelope tracking (ET) technique.To enhance efficiency performances, the PA uses a harmonic control network with double composite right/left-handed transmission lines. The use of the ET technique also results in high efficiency for the modulated signals. For verifications, the inverse class-E PA is implemented with a 35-W GaN HEMT and tested using 3.5 GHz continuous wave (CW) and 802.16e WiMAX signals. With the CW signal, a peak drain efficiency of 79.0% with a power gain of 9.8 dB is achieved at a saturation output power of 45.6 dBm. With WiMAX signals, a drain efficiency of 37.8% with a power-added efficiency (PAE) of 33.6% is achieved at an average output power of 36 dBm, which is the 9.6 dB back-off power region, using the ET technique. After the DPD technique, the linearity significantly improved without decreasing efficiency. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:866–869, 2013; View this article online at wileyonlinelibrary.com. DOI: 10.1002/mop.27420

Design of Highly Efficient Three-Stage Inverted Doherty Power Amplifier

This letter reports the highly efficient three-stage inverted Doherty power amplifier (IDPA) using 30 W and 50 W Si LDMOSFETs. The characteristic impedances of the output combiner are derived to achieve high efficiency at a large back-off power (BOP). The output matching networks and offset lines of the carrier and peaking cells are used to modulate the load impedance. The transmission line in the input path of the carrier cell is inserted to adjust the delay among the carrier and peaking cells. The drain efficiency (DE) of 40.3% with a gain of 9 dB is achieved at output power of 42 dBm (8.5 dB BOP) and the DE above 40% is maintained in wide output range for a 2.14 GHz continuous wave signal. For a one-carrier WCDMA signal at an output power of 40 dBm (10.5 dB BOP), the DE of 35% with the gain of 9.2 dB is achieved.

GaN HEMT Based High Power and High Efficiency Doherty Amplifiers with Digital Pre-Distortion Correction for WiBro Applications

This paper presents high power and high efficiency Doherty amplifiers for 2.345 GHz wireless broadband (WiBro) applications that use a Nitronex 125-W (<TEX>$P_{3dB}$</TEX>) GaN high electron mobility transistor (HEMT). Two- and three-way Doherty amplifiers and a saturated Doherty amplifier using Class-F circuitry are implemented. The measured result for a center frequency of 2.345 GHz shows that the two-way Doherty amplifier attains a high <TEX>$P_{3dB}$</TEX> of 51.5 dBm, a gain of 12.5 dB, and a power-added efficiency (PAE) improvement of about 16 % compared to a single class AB amplifier at 6-dB back-off power region from <TEX>$P_{3dB}$</TEX>. For a WiBro OFDMA signal, the Doherty amplifier provides an adjacent channel leakage ratio (ACLR) at 4.77 MHz offset that is -33 dBc at an output power of 42 dBm, which is a 9.5 dB back-off power region from <TEX>$P_{3dB}$</TEX>. By employing a digital pre-distortion (DPD) technique, the ACLR of the Doherty amplifier is improved from -33 dBc to -48 dBc. The measured result for the same frequency shows that the three-way Doherty amplifier, which has a <TEX>$P_{3dB}$</TEX> of 53.16 dBm and a gain of 10.3 dB, and the saturated Doherty amplifier, which has a <TEX>$P_{3dB}$</TEX> of 51.1 dBm and a gain of 10.3 dB, provide a PAE improvement of 11 % at the 9-dB back-off power region and 7.5 % at the 6-dB back-off region, respectively, compared to the two-way Doherty amplifier.

Analysis and Optimization of Transformer-Based Series Power Combining for Reconfigurable Power Amplifiers

Transformer-based series power combiners are analyzed within the context of reconfigurable, watt-level, wideband digital envelope tracking transmitters. A model is developed for designing and analyzing transformer-based switchable series combiners. This model takes into account losses in the windings and nonideal mutual coupling, as well as the effect of switching and scaling the input amplifiers on the combiner efficiency, input impedance, and power combining ratio. Optimum combining efficiency is derived for a combiner with scaled sources. Based on the developed model, a four-element 29.5-dBm power amplifier with 31% peak efficiency at 1.9 GHz, using a 1.5-V supply is designed and simulated in IBM 130-nm CMOS technology. The efficiency drops to 14% at 12 dB power back-off when elements are turned off. The amplifier maintains an output power >; 25 dBm from 1.8 GHz to 2.5 GHz. The studies presented in this paper can be extended to any series combiner implementation and any frequency range, which can be effective in the design of watt-level power amplifiers in submicrometer CMOS technologies.

A New Wideband Distributed Doherty Amplifier for WCDMA Repeater Applications

A new wideband distributed Doherty amplifier (WDDA) for wideband code division multiple access (WCDMA) repeater applications is reported. The distributed structure provides wideband performance while not needing an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -way splitter and combiner. The two-stage Doherty amplifiers achieve high gain and high efficiency. Also, the linearity of the WDDA is improved by the post-distortion using gate bias optimization of the Doherty amplifiers. For verification, the proposed WDDA is implemented using GaN HEMTs and tested with a one-carrier WCDMA signal at 2.14 GHz. From the measured results at an average output power of 36 dBm (10 dB back-off power), the WDDA shows an adjacent channel leakage ratio (ACLR) of - 45 dBc at plusmn 5 MHz offset with a total gain over 24 dB and a total power-added efficiency over 15% over a 160 MHz bandwidth.

Unequal-Cells-Based GaN HEMT Doherty Amplifier With an Extended Efficiency Range

This letter reports an extended GaN HEMT Doherty power amplifier (DPA). For high efficiency over a wide output power range, the DPA is designed using two cells with unequal saturation power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). A cell with lower P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> is used as the carrier cell. For experimental validations, the carrier and peaking cells are designed and implemented with 25 W GaN HEMTs at wide-band code division multiple access (WCDMA) of 2.14 GHz, and then show the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 41.3 dBm and 43.6 dBm, respectively. For the proposed DPA, the single-tone results show the power-added efficiency (PAE) of 50% at an output power of 37.3 dBm (9 dB back-off power from P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). For a one-carrier WCDMA signal, the PAE of 47.9% with an adjacent channel leakage ratio of -35.8 dBc is obtained at 37.3 dBm, which is 7.9% improvement compared to the conventional DPA. The PAE of 40% is maintained over an 11.4 dB back-off power.

Highly Linear and Efficient Microwave GaN HEMT Doherty Amplifier for WCDMA

A highly linear and efficient GaN HEMT Doherty amplifier for wideband code division multiple access (WCDMA) repeaters is presented. For better performance, the adaptive gate bias control of the peaking amplifier using the power tracking circuit and the shunt capacitors is employed. The measured one-carrier WCDMA results show an adjacent channel leakage ratio of −43.2 dBc at ±2.5-MHz offset with a power added efficiency of 40.1% at an average output power of 37 dBm, which is a 7.5 dB back-off power from the saturated output power.