Datapath Elements Research Articles

Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications

The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard version of the AMBA APB bus to connect peripherals and is primarily geared towards control and monitoring applications. This solution is a demonstrator of what can become a more complete fully radiation-tolerant SoC platform with a standardized interconnect and an IP block library, to serve as the starting point for future ASIC designs. The ASIP based approach targets more the design of data path elements and the use in data processing applications. The presented approach makes use of a commercial ASIP Designer EDA tool to demonstrate an integrated workflow to define, benchmark and optimize an ASIP for a specific use case, starting from a general-purpose processor.

Оценка влияния фазового шума элементов информационного тракта на показатели качества радиолокационного изображения (на примере опорного генератора)

Рассмотрен способ оценки влияния фазового шума элементов информационного тракта космического радиолокатора синтезированной апертуры на качество изображения. Разработана модель зависимости фазовой ошибки от спектра случайного шума опорного генератора с учётом задержки распространения сигнала и ширины доплеровского спектра. Определено влияние интегральной фазовой ошибки на качество радиолокационного изображения The article covers a method for evaluating of the data path elements phase noise effects the quality of synthetic aperture space radar image. A model of the phase error dependence the random noise spectrum of the reference generator is developed, taking into account the signal propagation delay and the width of the Doppler spectrum. The integral phase error influence the quality of the radar image is determined

Coarse-Grained Reconfigurable Computing with the Versat Architecture

Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

Reversible logic has been emerging as a replacement for conventional digital computers and has been found to be a promising technology for the future that can improve the quality of circuits in terms of power, speed, heat dissipation, life span, and input traceability. The new generation of quantum processors demands the efficient implementation of decimal data path elements in many commercial, financial, and Internet-based applications. Reversible binary-coded decimal multipliers are among the important circuits in quantum computers. In this approach, we propose a low-power reversible radix binary-coded decimal multiplier. The proposed methodology uses a novel 4221 reversible recorder gate to select precomputed constant multiples and binary to excess-six conversion reversible decimal adder for partial product compression. The proposed multiplier is designed with 180-nm application-specific integrated circuit technology using the Cadence EDA tool and is compared with state-of-the-art BCD algorithms designed using reversible gates. Experimental evaluations revealed that the proposed design demonstrates power and power-delay product reductions of 28% and 37%, respectively, compared to those of the best BCD algorithms implemented in reversible logic.

Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process

PurposeThe purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V.Design/methodology/approachIn this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates.FindingsThe proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP.Originality/valueIn arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems

Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180[Formula: see text]nm, 90[Formula: see text]nm and 45[Formula: see text]nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo [Formula: see text] and [Formula: see text] signed arithmetic modules are implemented.

Security enhancement for software defined network using game theoretical approach

Software Defined Networking (SDN) is a new approach for network programmability, which refers to the ability to control, change, and manage network behavior dynamically through software via open interfaces in contrast to relying on closed boxes and proprietary defined interfaces. It envisions the plan, deploy the critical service, performance and IT management upgrades for the utilization of 5th generation technology. The SDN framework enables centralized control of data path elements independently of the network technology used to connect these devices that can originate from different vendors. The centralized control embeds all the intelligence and maintains a network wide view of the data path elements and links that connect them. The novel approach will enhance the security for software defined network using the concept of game theory approach. The experimental results and analysis show that this approach has palpable advantages to enhance security in SDN.

Optimizing the network edge for flexible service provisioning

The virtualization of network resources provides unique flexibility in service provisioning in most levels of the network stack. Softwarization of the network control and operation (SDN) is a key enabler of that development. Starting from the network core, SDN is a dominant trend in the evolution of network architectures with increased emphasis recently on the network edge. I will present some recent results in this area starting with a study on migration from legacy networking to SDN enabled network modules. The tradeoff between the benefits of SDN upgrades and the cost of deployment is addressed and captured by an appropriate sub-modular function that allows to optimize the penetration pace of the technology. Validation on some real world network topologies and traffic matrices will be presented as well. Then we move our attention to the network periphery. A wireless multi-hop extension at the network edge is considered and the problem of enabling SDN is addressed via replication of SDN controllers. The delay constraints of the controlled data-path elements is appropriately modeled and the problem of locating the controllers is addressed via optimization and a proof-of concept implementation. An alternate approach is considered then for the wireless network where we assume coexistence of SDN enabled components with network islands operating under distributed adhoc routing protocols. The trade-off of the coexistence is studied and the impact of SDN penetration is evaluated. Some paradigms of collaborative network services are presented finally as they are enabled by the above architectural evolution.

Protecting Home User Devices with an SDN-Based Firewall

Internet-connected consumer electronics marketed as smart devices (also known as Internet-of-Things devices) usually lack essential security protection mechanisms. This puts user privacy and security in great danger. One of the essential steps to compromise vulnerable devices is locating them through horizontal port scans. In this paper, we focus on the problem of detecting horizontal port scans in home networks. We propose a software-defined networking (SDN)-based firewall platform that is capable of detecting horizontal port scans. Current SDN implementations (e.g., OpenFlow) do not provide access to packet-level information, which is essential for network security applications, due to performance limitations. Our platform uses FleXight, our proposed new information channel between SDN controller and data path elements to access packet-level information. FleXight uses per-flow sampling and dynamical sampling rate adjustments to provide the necessary information to the controller while keeping the overhead very low. We evaluate our solution on a large real-world packet trace from an ISP and show that our system can identify all attackers and 99% of susceptible victims with only 0.75% network overhead. We also present a detailed usability analysis of our system.

Design of Efficient Reversible BCD Adder–Subtractor Architecture and Its Optimization Using Carry Skip Logic

In the present era, reversible logic designs play a very critical role in nanotechnology, low power complementary metal-oxide semiconductor (CMOS) designs, optical computing and, especially, in quantum computing. High power dissipation and leakage current in deep submicron technologies is a severe threat in applications created today. As a consequence, design of datapath elements in reversible logic has gained much importance. In this study, a novel design of binary coded decimal (BCD) adder/subtractor in reversible logic has been proposed. As a further optimization of the proposed reversible decimal design, carry skip (CSK) logic is used for reversible ripple carry adder stages. This reduces delay but at the expense of little hardware. The proposed BCD adder/subtractor and its optimized version are designed using structural VHDL and simulated using ModelSim 6.3f. Performance analysis reveals that the proposed BCD design demonstrates reductions in gate count, garbage outputs and constant inputs of 30.5%, 46% and 28%, respectively, and its optimized version exhibits 19.4%, 32.4% and 16% reductions in gate count, garbage outputs and constant inputs compared to the design in Ref. 14 [V. Rajmohan, V. Renganathan and M. Rajmohan, A novel reversible design of unified single digit BCD adder–subtractor, Int. J. Comput. Theor. Eng. 3 (2011) 697–700].

Efficient Audio Filter Using Folded Pipelining Architecture Based on Retiming Using Evolutionary Computation

It is important in digital signal processing (DSP) architectures to minimize the silicon area of the integrated circuits. This can be achieved by reducing the number of functional units such as adders and multipliers. In literature, folding technique is used to reduce the functional units by executing multiple algorithm operations on a single functional unit. Register minimization techniques are used to reduce the number of registers in a folded architecture. Retiming is a technique that needs to be performed before applying folding. In this paper, retiming is performed based on nature inspired evolutionary computation method. This technique generates the database of solutions from which best solution can be picked for folding further. As a part of this work, an efficient folded noise removal audio filter prototype is designed as an application example using evolutionary computation-based retiming and folding with register minimization. Folding technique will however increase the number of registers while multiplexing datapath adder and multiplier elements. Register minimization technique is used after folding to reduce the number of registers. After obtaining retimed, folded filter architecture, low level synthesis is performed which involves mapping of datapath adder and multiplier blocks to actual hardware. Various architectures of adders and multipliers are compared in area-power-performance space and depending on the user defined constraint, folded architecture with specific combination of data path elements is mapped on to hardware. A framework is designed in this paper to automate the entire process which reduces the design cycle time. All the designed filters are targeted for ASIC implementation. The results are compared and are provided as part of simulation results.

Splitarchitecture: SDN for the carrier domain

The concept of SDN has emerged as a way to address numerous challenges with traditional network architectures by decoupling network control and forwarding. So far, the use cases for SDN mainly targeted data-center applications. This article considers SDN for network carriers, facing operation of large-scale networks with millions of customers, multiple technologies, and high availability demands. With specific carrier-grade features such as scalability, reliability, flexibility, modularity, and virtualization in mind, the SPARC EU project has developed the SPARC SplitArchitecture concept. The SplitArchitecture control plane allows hierarchical layering of several control plane layers which can be flexibly mapped to data plane layers. Between control layers open interfaces are used. Furthermore, SplitArchitecture proposes an additional split of forwarding and processing functions in data path elements, enabling switch based OAM functionality and handling of tunneling techniques. The SplitArchitecture concept is evaluated in a prototype demonstrating an SDN version of BRAS: the floating BRAS. The floating BRAS allows creation of residential Internet access services with dynamically managed BRAS instances. The demo is based on a controller enabling protected MPLS transport connections spanning SDN-controlled aggregation and IP/MPLS-based core domains. The prototype showcases how SplitArchitecture enables virtualization of service nodes in an SDN-controlled network, leading to increased flexibility in configuration and placement of service creation functions. Overall, the results show that it is technically and economically beneficial to apply SDN, and specifically the SplitArchitecture concept, to the carrier domain.

Energy Efficient Multi-Core Processing

This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time minimal architectural synthesis technique to achieve greater energy and area efficiency whilst maintaining performance. The picoMIPS architecture is presented, inspired by the MIPS, as an example of a minimal and energy efficient processor. The picoMIPS is a variable architecture RISC microprocessor with an application-specific minimised instruction set. Each implementation will contain only the necessary datapath elements in order to maximise area efficiency. Due to the relationship between logic gate count and power consumption, energy efficiency is also maximised in the processor therefore the system is designed to perform a specific task in the most efficient processor-based form. The principles of the picoMIPS processor are illustrated with an example of the discrete cosine transform (DCT) and inverse DCT (IDCT) algorithms implemented in a multi-core context to demonstrate the concept of minimal architecture synthesis and how it can be used to produce an application specific, energy efficient processor.

Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques

The domain of inexact circuit design, in which accuracy of the circuit can be exchanged for substantial cost (energy, delay, and/or area) savings, has been gathering increasing prominence of late owing to a growing desire for reducing energy consumption of the systems, particularly in the domain of embedded and (portable) multimedia applications. Most of the previous approaches to realizing inexact circuits relied on scaling of circuit parameters (such as supply voltage) taking advantage of an application’s error tolerance to achieve the cost and accuracy trade-offs, thus suffering from acute drawbacks of considerable implementation overheads that significantly reduced the gains. In this article, two novel design approaches called Probabilistic Pruning and Probabilistic Logic Minimization are proposed to realize inexact circuits with zero hardware overhead.Extensive simulations on various architectures of critical datapath elements demonstrate that each of the techniques can independently achieve normalized gains as large as 2x--9.5x in energy-delay-area product for relative error magnitude as low as 10 − 4% --8% compared to corresponding conventional correct circuits.

중학교 정보 교과서에 제시된 중앙처리장치 내용 문제점 분석 및 개선 방안

2007년 개정 교육과정에서 컴퓨터 교육은 컴퓨터 과학의 원리와 개념을 배울 수 있는 내용을 강화하였다. 따라서 정보 교과서는 빠르게 발전하고 있는 컴퓨터 과학의 최신 흐름을 정확하고 일관되게 반영할 필요가 있다. 하지만 현재 중학교 정보 교과서에 제시된 중앙 처리 장치의 구성 요소에 대한 내용은 교과서마다 차이를 보여 정확성과 일관성이 결여되어 있다. 본 연구는 컴퓨터 구조 및 동작의 역사적, 기술적 접근을 통해 교과서 내용의 오류를 파악하고 개선 방안을 제시하였다. 연구 결과, 현재 컴퓨터 시스템의 중앙처리장치는 데이터패스와 제어 장치로 구성되었다고 기술하는 것이 바람직하다. 데이터패스는 명령어의 수행에 따라 데이터의 연산 또는 데이터를 일시적으로 저장하는 기능을 수행하며 메모리, 레지스터, 연산 장치, 가산기 등으로 구성된다. 제어 장치는 명령어의 수행에 따라 데이터패스, 주기억 장치, 입출력 장치 등의 동작유형을 결정한다. 하지만 어려운 전문 용어의 사용이 인지 발달 수준이 낮은 학습자의 학습을 저해할 수 있기 때문에 본 연구에서는 데이터패스와 제어 장치 대신 '연산부'와 '제어부'라는 표현을 사용할 것을 제안한다. The School Curriculum amend in 2007 mandates the contents from which students can learn the principles and concepts of computer science. Computer Science is one of the most rapidly changing subjects, and the Informatics textbook should accurately explain the basic principles and concepts based on the latest technology. However, we found that the middle school textbooks in circulation lack accuracy and consistency in describing CPU. This paper attempted to discover the root-cause of the fallacy and suggest timely and appropriate explanation based on the historical and technical analysis. According to our study, it is appropriate to state that CPU is composed of datapath and control unit. The Datapath performs operations on data and holds data temporarily, and it is composed of the hardware components such as memory, register, ALU and adder. The Control unit decides the operation types of datapath elements, main memory and I/O devices. Nevertheless, considering the technological literacy of middle school students, we suggest the terms, 'arithmetic part' and 'control part' instead of datapath and control unit.

Implementation of comprehensive address generator for digital signal processor

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log 2 N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.

TU-B-220-02: Microbeamforming for Large-Aperture Ultrasound Transducers

The Philips X6-1 xMatrix ultrasound transducer, introduced in 2010, is a novel 9,212 element, fully sampled 2D array for general imaging ultrasound applications. The elements of the array are fabricated directly onto an integrated circuit (IC) within the transducer, which processes and beamforms signals in real-time. This talk will review general concepts related to sub-array processing (i.e. “microbeamforming”) and how these concepts were applied to the design of the X6-1 transducer. Basic microbeamformer data path elements will be discussed, as well as the clinical significance of various operating parameters. Educational Objectives: 1. Review sub-array beamforming techniques, 2. Discuss imaging modes & scan formats for 3D ultrasound, 3. Discuss clinical significance of the X6-1 transducer.

Design Space Exploration of Split-Path Data Driven Dynamic Full Adder

This paper presents the design, the analysis and the complete characterization of a novel split-path Data Driven Dynamic (sp-D3L) full adder cell in IBM’s 65 nm CMOS process. The split path D3L design style derived from standard D3L allows the design of high speed dynamic circuits without the power overhead of the clock tree while providing significantly higher performance than the D3L due to reduced capacitance at the pre-charge node. To demonstrate the performance benefits of the new split-path dynamic approach, we present comparison of the proposed adder with conventional static and dynamic adder cells. All the adder circuits were characterized for speed, power, area, noise margins, supply voltage scaling as well as fan-out capabilities. To evaluate the combined impact of load driven by the adder and load presented by the adder to the driving circuit, a combined fan-infan-out analysis with varying loads was also performed. Monte Carlo simulations were performed to evaluate the reliability of the adder design against random process, voltage and temperature variations. To compare with state of the art, we also performed a comparison of our proposed adder with several low power as well as high performance adders proposed recently in literature. Furthermore, to simulate the behavior of the adder in data path elements, we built ripple carry adders of varying lengths using the proposed adder. The new design was found to achieve from 16% to 27% performance advantages over its static and dynamic counterparts at nominal supply voltage. With supply voltage scaled from 1 V to 0.8 V, the adder shows 12%, 34% and 39% PDP advantage over domino, static and conventional D3L designs respectively. Fan-out analysis showed the adder to perform with 11% to 41% better PDP than the others at worst case FO32 loading.

Low-power data representation

A method of changing a data representation to reduce the switching activity from datapath elements is described. The proposed method finds a low-power data representation so that more frequently consecutive data values have a smaller Hamming distance between their binary codes. The experimental results show that a switching activity reduction of up to 22.6% over a standard data representation scheme can be achieved.

A circuit-driven design methodology for video signal-processing datapath elements

The programmable video signal processor (VSP) is an important category of processors for multimedia systems. Programmable video processors combine the flexibility of programmability with special architectural features that improve performance on video processing applications. VSPs are typically multiple processors with several processing elements (PEs) and a parallel memory system. This paper focuses on the architectural design of the PE's in a video processor and shows how technology and circuit parameters influence the structure of the datapath and, hence, the overall architecture of a programmable VSP. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture and present a method whereby the conceptual organization of the PEs-the number of PEs, pipelining of the datapath, size of the register file, and number of register ports-can be evaluated in terms of a target set of applications before a detailed design is undertaken. We use motion-estimation and discrete cosine transform as example applications to illustrate how various technology parameters affect the architectural design choices. We show that the design of the register file and the datapath-pipeline depth can drastically affect PE utilization and, therefore, the number of PEs required for different applications. Our results demonstrate that pursuing the fastest cycle time can greatly increase the silicon area which must be devoted to PEs, due to both increased pipeline latency and reduced register file bandwidth.