Datapath Design Research Articles

Challenges and Solutions in High-Speed SerDes Data Path Design

Modern high-performance communication systems require high-speed Serializer/Deserializer (SerDes) data path design to meet the growing demand for data throughput and reliability due to technological advancements and data-intensive applications. This research article examines the complex problems of designing high-speed SerDes data routes and suggests novel solutions. Data fidelity across high-speed channels requires signal integrity, the first key difficulty. Attenuation, crosstalk, and EMI may degrade SerDes signal performance. Advanced methods like equalization, impedance matching, and effective shielding mitigate these impacts. Equalization, including feedforward and feedback methods, reduces channel losses and distortions, enhancing signal quality. Power consumption is another major issue as data rates and system complexity rise. Power-hungry high-speed SerDes circuits cause thermal management and energy efficiency difficulties. Adaptive power management, low-power design, and new materials with higher thermal performance and lower power dissipation are discussed in the study. Design complexity is another issue in high-speed SerDes data route design. High-precision timing and synchronization and many component integration in a small area need advanced design tools and methods. The study emphasizes simulation and modeling for complexity management and design for testability (DFT) for full verification and debugging.

Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector

This paper presents a security aware design methodology to design secure generalized likelihood ratio test (GLRT) hardware intellectual property (IP) core for electrocardiogram (ECG) detector against IP piracy and fraudulent claim of IP ownership threats. Integrating authentic (secure version) GLRT hardware IP core in the system-on-chip (SoC) of ECG detectors is paramount for reliable operation and estimation of ECG parametric data, such as Q wave, R wave and S wave (QRS) complex detection. A pirated GLRT hardware IP integrated into an ECG detector may result in an unreliable/erratic estimation of ECG parametric data that can be hazardous and fatal for the end patient. The proposed methodology presents an integrated design flow to secure micro GLRT and GLRT cascade hardware IP cores for the ECG detector, using the colored interval graph (CIG) framework based fingerprint biometric, during high level synthesis (HLS). The proposed approach integrates a fingerprint biometric based security constraint generation process for securing the GLRT hardware IP core. This paper also presents a secure register transfer level (RTL) datapath design corresponding to micro GLRT and GLRT cascade hardware IP cores with embedded IP vendor's fingerprint. The proposed secure GLRT hardware IP core embedded with fingerprint biometric achieves superior results in terms of probability of coincidence and tamper tolerance than other security approaches. More explicitly, the proposed approach reports a significantly lower value of probability of coincidence and stronger value for tamper tolerance. Further, the proposed approach incurs zero design cost overhead.

A Design Flow and Tool for Avoiding Asymmetric Aging

This article proposes a design flow and tool to deal with asymmetric aging in datapath designs by employing automated engineering change order flow.

Performance Evaluation of Datapath designs using FinFET and MOSFET

The VLSI Technology has been progressing significantly and the circuits which consume less power become major concern factor for designing todays ICs for Microprocessors and other various systems components. The Datapath is important part of a system. Adders, multipliers, and shift registers are the major components of data path unit of ALU. Almost all digital circuits and chips are made of MOSFET as the basic switching element. But same MOSFET suffers due to Short Channel Effects (SCEs) when scaled down to nano regime, which has promoted multigate device called FinFET. And this FinFET device overcomes the SCEs at technology nodes. In this paper 28T and 16T MOSFET and FinFET based full adders are designed. Using adders, 4x4 array multiplier is designed using both MOSFET and FinFET technology along with it Serial in Serial out shift register designs. The circuits designed based on MOSFET and FinFET are analyzed in terms of power and delay at various nodes. From the software characterization and analysis, it is understood that FinFET based circuits promise better performance at lower technology nodes like 22nm and 14nm than higher technology nodes in MOSFET like 250nm, 180nm, 90nm and 45nm. Hence FinFET becomes a promising device for future IC technology.

Lightweight ANU-II block cipher on field programmable gate array

Nowadays the number of embedded devices communicating over a network is increasing. Thus, the need for security appeared. Considering various constraints for the limited resources devices is very important. These constraints include power, memory, area and latency. A perfect environment for satisfying requirements of security in limited resources devices is lightweight cryptography. A recent lightweight algorithm that has a low area and high throughput which is the ANU-II block cipher. Many technologies like the internet of things (IoT) needed lightweight hardware architectures to provide security for it. In IoT issues like the size of memory, power consumption and smaller gate counts need to take care of by using lightweight cryptography. This paper presents hardware lightweight data path implementation for the ANU-II algorithm using field programmable gate array (FPGA). This paper presents a hardware implementation of a 64-bit ANU-II block cipher. Also, this research presents comparisons based on various design metrics among our data path for the ANU-II cipher and other existing data path designs. The result of the proposed design shows a high throughput of 1502.31, 1951.86, and 2696.47 Mbps. Also, it shows the high efficiency of 7.0201, 31.9977, and 10.6579 Mbps/slice as compared to other ciphers in this paper.

An Adaptable and Scalable Generator of Distributed Massive MIMO Baseband Processing Systems

This paper presents an algorithm-adaptable, scalable, and platform-portable generator for massive multiple-input multiple-output (MIMO) baseband processing systems. This generator is written in Chisel hardware construction language, and produces instances that implement distributed massive MIMO base station (BS) processing, including channel estimation and beamforming. The generator can be reused for different MIMO systems and hardware datapath designs by changing the parameters. The generator is paired with a Python-based system simulator, which incorporated together can emulate a system testing various baseband signal processing algorithms. The field programmable gate array (FPGA) emulation is performed with generated instances using various parameter values. To demonstrate the algorithmic adaptability, a Golay-sequence-based channel estimation method, a beamspace calibration method, and a channel denoising algorithm are evaluated across a range of channel models. The performance of the generator, necessity of the algorithmic adaptability, and ease of hardware generation are evaluated and discussed. The emulated register-transfer level (RTL) implementation with different system parameters shows that with beamspace methods, the demodulation error vector magnitude is improved by up to 29.8%.

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors. Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors. Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

Design of filter for image de-noising using discrete wavelet transform for ASIP

Application specific instruction-set processors (ASIP) is a customised processor for user specific application. Though a significant research has been done on this, still it is most promising technology, due to lack of efficient methodologies for designing the processor configuration according to the applications. Again ASIP solution explores the trade-off between the dedicated hardware design and flexibility among software. It endeavours to fulfil the functionality of an algorithmic with low power costs and less complexity. In this paper, an approach is considered to design a processor for image de-noising. The design of suitable filter is an important task for the transmission and real-time processing. Designing ASIPs requires a suitable design of custom data path simultaneously modify the instruction-set, decoder including the compiler. We present an ASIP based on custom architecture design using the discrete wavelet transform (DWT) as a filter. It starts with the general purpose data path like MIPS. It customises the data path iteratively for better power utilisation, usable area and performance. All the experiments have been synthesised using Xilinx FPGA and also verified in Spartan board. The subjective evaluations of the filter is analysed through various figures. Further it is implemented in HDL to support the customised processor.

Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

Since the dawn of the Internet of Things (IoT), data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power, encryption and decryption need to be implemented at the transmitting and receiving ends, respectively, using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition, and the results are compared on every performance metric. Unlike previous ANU architectures, the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs, ANU cipher proves to be the obvious choice for implementing security in extremely resource-constrained systems.

Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors

In a modern world for non numeric applications, out-of-order super scalar processors are designed to achieve higher performance. Unfortunately the improvement in the performance has lead to the increase in the chip power and energy dissipation. The load/store queue is a one of the major power consuming unit in the data path design during dynamic scheduling. Load/store queue is designed to absorb busts in cache access and maintain the order of memory operations by keeping all in-flight memory instruction in program order. The proposed technique aims at reducing both dynamic and static power dissipation in the load/store queue (LQ/SQ) by using power-gating technique and priority encoder. Through this implementation, the least amount of redesign, verification efforts, lowest possible design risk, least hardware overhead is achieved without significant impact on the performance.

Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors

In a modern world for non numeric applications, out-of-order super scalar processors are designed to achieve higher performance. Unfortunately the improvement in the performance has lead to the increase in the chip power and energy dissipation. The load/store queue is a one of the major power consuming unit in the data path design during dynamic scheduling. Load/store queue is designed to absorb busts in cache access and maintain the order of memory operations by keeping all in-flight memory instruction in program order. The proposed technique aims at reducing both dynamic and static power dissipation in the load/store queue (LQ/SQ) by using power-gating technique and priority encoder. Through this implementation, the least amount of redesign, verification efforts, lowest possible design risk, least hardware overhead is achieved without significant impact on the performance.

IP Core Steganography for Protecting DSP Kernels Used in CE Systems

Intellectual Property (IP) core protection of Digital Signal Processing (DSP) kernels is an important subject of research for Consumer Electronics (CE) systems. An IP core may be prone to piracy, forgery and counterfeiting. The need of the hour is developing effective technique that is robust and incurs low overhead to detect IP core infringement. This paper presents a novel ‘IP core steganography’ methodology for DSP kernels that is capable of detecting IP piracy. The proposed methodology is capable of implanting concealed information into the existing IP core design of DSP datapath without using any external signature, to reflect the IP core ownership. The presented ‘IP core steganography’ methodology is non-intuitive in nature indicating that the intended secret information does not attract attention to itself from an adversary’s perspective. The implanted information incurs almost no design overhead and yields lower design cost than signature-based IP core protection techniques. Further, in the presented approach the amount of concealed information embedded is fully designer controlled through a ‘thresholding’ parameter, unlike signature-based techniques where signature pattern impacts the robustness and overhead. Results of proposed approach yielded lower cost and stronger proof of authorship compared to a signature-based approach.

Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation

A novel design of a hybrid Full Adder (FA) using Pass Transistors (PTs), Transmission Gates (TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is presented. Performance analysis of the circuit has been conducted using Cadence toolset. For comparative analysis, the performance parameters have been compared with twenty existing FA circuits. The proposed FA has also been extended up to a word length of 64 bits in order to test its scalability. Only the proposed FA and five of the existing designs have the ability to operate without utilizing buffer in intermediate stages while extended to 64 bits. According to simulation results, the proposed design demonstrates notable performance in power consumption and delay which accounted for low power delay product. Based on the simulation results, it can be stated that the proposed hybrid FA circuit is an attractive alternative in the data path design of modern high-speed Central Processing Units.

Design and Implementation of novel datapath designs of lightweight cipher RECTANGLE for resource constrained environment

The advancements in IoT and manufacturing techniques has given rise to the use of small embedded devices such as RFIDs, sensor nodes and smart cards. Due to hardware and software constraints, the standard encryption algorithm like AES cannot be used for encryption of such devices. Thus lightweight block ciphers like PRESENT, LED, MIDORI, and RECTANGLE were proposed. RECTANGLE cipher uses Bit-slice technology to make it suitable for the extremely constrained environment. For achieving high efficiency and good performance, along with the selection of the cipher, it is important to implement it with the right datapath. In this paper, we have focused on the hardware implementation of block cipher RECTANGLE with different novel datapaths. In this paper, we have proposed, implemented and evaluated 5 most efficient datapaths of different data bus size of RECTANGLE cipher. All these datapaths are implemented on different FPGA platforms with the same implementation conditions and the results are compared on every performance metric. Based on the device and desired performance metrics, one can choose the best-suited architecture for their application. This paper presents a novel architectures of cipher RECTANGLE suitable for the constrained environment. We have also compared the metrics of the proposed architectures with that of other standard lightweight block ciphers to obtain a better insight on the resourcefulness of the proposed datapaths.

ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs

Convolution Neural Networks are now widely used in image processing, object detection, video detection, and other classification tasks. Thus the acceleration of CNN is also widely researched for its complex computation features and data dependence. To achieve high energy efficiency, we proposed a CNN accelerator with approximate computing techniques. In this paper, two main aspects are studied: the hardware-compatible network compression algorithms, and the approximate computing units and architectures with hardware resource scheduling strategies. For the algorithm approximation part, we introduce a dynamic layered CNN structure for different scales of input, the convolution kernel shrinking strategy with layer-by-layer quantization to compress networks, and the Winograd Minimum Filter algorithm to decrease operations in convolution layers. For the architecture part, two types of approximate multipliers are innovated as iterative multipliers, and multi-port SRAM integrated LUT based multipliers. Approximate adders with error correction logic are also designed. Based on the approximate computing units, the Convolution Neural Processing Unit named CNPU is proposed with reconfigurable datapath designs for the mapping of different tasks. By the work on the algorithm, the CNPU architecture and the datapath design, we propose a high energy efficient reconfigurable CNN accelerator with approximate computing named ARA (Approximate computing based Reconfigurable Architecture). Implemented under TSMC 45 nm process, our accelerator achieves 1.92TOPS/W@ 1.1 V, 200 MHz and 3.72TOPS/W@ 0.9 V, 40 MHz in energy-efficiency, which is 1.51 ∼ 4.36 times better than the state-of-the-art accelerators.

Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design

DOI : 10.26650/electrica.2018.15101 Set partitioning in hierarchical trees (SPIHT) is an efficient algorithm which is used for the image compression widely. SPIHT operates sequentially so, its parallel implementation is difficult. In this study, the SPIHT algorithm is improved for providing that it is suitable for the parallel processing applications, and the corresponding pipelined datapath is designed for the proposed enhanced SPIHT algorithm. The datapath is designed to have three stages as preprocessing, list generation and output stream. In the preprocessing stage, the flags which are supports the list generation stage are constituted. List of insignificant sets (LIS), list of insignificant pixels (LIP) and list of significant pixels (LSP) are formed in list generation stage. These lists contain the bit values which generate the output bit stream. The performance of the improved datapath design has been tested by compressing different images, and the obtained results are given. Cite this article as: Cekli S, Akman A. Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design. Electrica, 2019; 19(1): 29-36.

Building an Extensible Open vSwitch Datapath

The virtual switch is the cornerstone of the today's virtualized data center. As all traffic to and from virtual machines or containers must pass through a vSwitch, it is the ideal location for network configuration and policy enforcement. The bulk of Open vSwitch functionality is platform-agnostic and portable. However the datapath, which touches every packet, is unique to each supported platform. Maintaining each datapath requires duplicated effort and the result has been inconsistent support of features across platforms. Even on a single platform, the features supported by a particular kernel version can vary. Further, datapath functionality must be broadly useful which prevents having application-specific features in the fast path. eBPF, extended Berkeley Packet Filter, enables userspace applications to customize and extend the Linux kernel's functionality. It provides flexible platform abstractions for network functions, and is being ported to a variety of platforms. This paper describes the design, implementation, and evaluation of an eBPF-based extensible OVS datapath. The eBPF OVS datapath delivers the equivalent functionality of the existing OVS kernel datapath, while significantly reducing development pain points around maintainability and extensibility. We demonstrate that these benefits don't necessarily have a trade off in regards to performance, with the eBPFbased datapath showing negligible overhead compared to the existing kernel datapath.

Reducing the Performance Gap between Soft Scalar CPUs and Custom Hardware with TILT

By using resource sharing field-programmable gate array (FPGA) compute engines, we can reduce the performance gap between soft scalar CPUs and resource-intensive custom datapath designs. This article demonstrates that Thread- and Instruction-Level parallel Template architecture (TILT), a programmable FPGA-based horizontally microcoded compute engine designed to highly utilize floating point (FP) functional units (FUs), can improve significantly the average throughput of eight FP-intensive applications compared to a soft scalar CPU (similar to a FP-extended Nios). For eight benchmark applications, we show that: (i) a base TILT configuration having a single instance for each FU type can improve the performance over a soft scalar CPU by 15.8 × , while requiring on average 26% of the custom datapaths’ area; (ii) selectively increasing the number of FUs can more than double TILT’s average throughput, reducing the custom-datapath-throughput-gap from 576 × to 14 × ; and (iii) replicated instances of the most computationally dense TILT configuration that fit within the area of each custom datapath design can reduce the gap to 8.27 × , while replicated instances of application-tuned configurations of TILT can reduce the custom-datapath-throughput-gap to an average of 5.22 × , and up to 3.41 × for the Matrix Multiply benchmark. Last, we present methods for design space reduction, and we correctly predict the computationally densest design for seven out of eight benchmarks.

A Data Path Design Tool for Automatically Mapping Artificial Neural Networks on to FPGA-Based Systems

Artificial Neural Networks (ANNs) are usually implemented as software running on general purpose computers. On the other hand, when software implementations do not provide sufficient performance, ANNs are implemented as hardware on FPGA based systems for performance enhancement. Mapping ANNs to FPGAs is a time consuming and error prune process. In this study, a novel data path design tool, ANNGEN, has been proposed to help automate mapping ANNs to FPGA based systems. ANNGEN accepts ANN definitions in a NetList form. First, it parses and analyzes given NetList. Second, it checks the availability of the neurons. If all the neurons required by the NetList are available in its neuron Library, ANGENN performs the design procedure and produces VHDL code for the given NetList. ANNGEN has been tested with several different test cases, and it is observed that it is able to successfully generate VHDL codes for given ANN NetLists. Our practice with ANNGEN has showed that it effectively shortens the time required for implementing ANNs on FPGAs. It also eliminates the need for expert people. Additionally, ANNGEN produces error free code; thus, the debugging stage is also eliminated.