Dataflow Specification Research Articles

Model-driven development for functional correctness of avionics systems: a verification framework for SysML specifications

AbstractCurrently, the most widespread software quality assurance methods in the avionics domain are semi-automated reviews and testing. However, their effort grows disproportionately to the size of the system under development. Also, these methods cannot achieve exhaustive coverage due to the complexity of today’s avionics systems and their potentially infinite set of combinations of possible inputs and system states. Furthermore, the later software issues are detected in the development process, the more expensive it is to fix them. To overcome these issues, a model-driven verification approach for modeling and analyzing avionics systems in early phases of the development is presented. To this end, semantics is given to SysML v2 models by a mapping to a theorem prover encoding. The development of a dedicated SysML v2 profile supporting event-driven data flow specifications, the encoding of corresponding structures in the theorem prover Isabelle, and a generator creating theorems from SysML v2 models are presented. The approach is evaluated by formally proving a representative liveness property of a hierarchical system model from the avionics domain. Since liveness properties can be negated only by infinite data sequences and thus cannot be covered exhaustively by testing, this case study demonstrates the added value for meeting typical safety requirements in the avionics domain. The results can be transferred from avionics to other domains, as well.

Real-Time Fixed Priority Scheduling Synthesis using Affine DataFlow Graphs: from Theory to Practice

The major drawback of using static schedules to execute dataflow applications is their high inflexibility. In real-time systems, periodic schedules make it easier to assert safety guarantees and to decrease the schedule size, but their characteristics remain hard to compute. This article presents an approach to automatically generate fixed priority schedules from a dataflow specification. To do so, precedence dependencies between actors in the dataflow graphs are abstracted, as well as the task periods, by using affine relations . This abstraction allows us to synthesize schedules efficiently considering two main objectives: the maximization of throughput and the minimization of buffer sizes. Given a dataflow graph to execute in a real-time environment, we transform it into an Affine DataFlow Graph (ADFG) and compute the task priorities, their mapping, the number of delays in the buffers, and the buffer sizes. This article is the first to present an overview of both theoretical and practical aspects of ADFG. On the theoretical side, it presents corrections and improvements on the fixed priority case. On the practical side, benchmark evaluations demonstrate the robustness and maturity of the approach that our scheduling synthesizer implements. Synthesized schedules are evaluated by using scheduling simulation and real-time implementation. Last but not least, the synthesized periods reach the optimal throughput if enough processors are available, and most of the time the periods reach the maximal processor utilization factor in the uni-processor case. Moreover, execution time of the synthesis is about only one second for the main proposed algorithms.

Verification of concurrent code from synchronous specifications

• Methodology to generate concurrent code automatically from SIGNAL specifications. • New clock calculus method to explore the clock relations among signals. • Verification of concurrent code from SIGNAL specifications. The synchronous language SIGNAL is a formal specification formalism for developing safety-critical real-time systems. It is a multi-clocked data-flow modeling language suitable for specifying deterministic concurrent behaviors. Its model of computation and communication very well matches recent trends to utilize multi-core processors for executing real-time systems, by taking advantage of its concurrent semantics. The SIGNAL compiler generates code from data-flow specifications while analyzing and verifying safety properties of the system under design: deadlock-freedom, determinism. However, most of recent works have focused on generating sequential code from SIGNAL. Choosing the parallel library OpenMP as the target, this paper proposes a methodology to generate and verify concurrent code automatically from SIGNAL specifications. This is done by first exploring clock relations among signals by application of a so-called clock calculus. Then, specifications are translated into EDGs (Equation-Dependency Graphs) to analyze global data-dependency relations. An EDG is then partitioned into concurrent tasks to help explore parallelism in the original specification while preserving its semantic. Combined with clock relations, parallel tasks are finally mapped onto the OpenMP structures. The proposed approach is illustrated by a realistic case study.

Efficiently Switchable Context-Aware Dataflow Adaptation Technique for Low-Power Multi-Core Embedded Systems

Today’s embedded systems operate under increasingly dynamic conditions. First, computational workloads can be either variable by nature or adjustable. Moreover, as many devices are battery-powered, it is common to have runtime power management technique, which results in dynamic power budget. This paper presents a design methodology for multi-core systems, based on dataflow specification, that can deal with various contexts. We optimize the original dataflow considering various working conditions, then, autonomously adapt it to a pre-defined optimal form in response to context changes. Such context changes at runtime might cause non-negligible delay or power budget violation. In order to overcome them, an efficient mode switching method is proposed. We show the effectiveness of the proposed technique with a real-life case study, stereo-vision, and synthetic benchmarks.

Data map – method for the specification of data flows within production

Digitization of production offers potentials e.g. in reducing throughput-times and increasing productivity. MES and ERP systems can be the central hub for organizing, analyzing and processing enterprise and manufacturing data. Introducing these systems requires clear requirement-definition, since 60% of errors occur here. Even for existing production systems, the successful leverage of data potentials requires a systematic overview of data sources, processing units and sinks.We propose a Data Map to address these problems. It visualizes data flow between data sources and software systems, considering their properties and process context. We demonstrate the application in a project to identify requirements for selecting an ERP System.

Dataflow object detection system for FPGA‐based smart camera

Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.

Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy

Modern embedded systems, to accommodate different applications or functionalities over the same substrate and provide flexibility at the hardware level, are often resource redundant and, consequently, power hungry. Therefore, dedicated design frameworks are required to implement efficient runtime reconfigurable platforms. Such frameworks, to challenge this scenario, need also to offer application specific support for power management. In this work, we adopt dataflow specifications as a starting point to feature power minimization in coarse-grained reconfigurable embedded systems. The proposed flow is composed of two subsequent steps: 1) the characterization of the optimal topological system specification(s) and 2) the identification of disjointed logic regions. These latter are then used to implement clock and power gating methodologies. The validity of this model-based approach has been proved over the reconfigurable computing core of a multi-functional coprocessor for image processing applications. Results have been assessed targeting both an ASIC 90 nm technology and a 45 nm one.

Actor Merging for Dataflow Process Networks

Dataflow process networks provide a versatile model of computation for specifying signal processing applications in a platform independent fashion. This attractive feature of dataflow has lately been realized in dataflow programming tools that allow synthesizing the same application specification as both fixed hardware circuits and as software for programmable processors. However, in practice, the specification granularity of the dataflow program remains an arbitrary choice of the designer. Dataflow specifications of the same application with equivalent I/O behaviour can range from a single dataflow actor to a very fine grained network composed of elementary processing operations. A very fine grained dataflow specification might result into a high performance implementation when synthesized as hardware, but might perform poorly when executed on a programmable processor. This article presents actor merging as one solution for this performance portability problem of dataflow programs. In contrast to previous work around actor merging, this article presents a methodology that can merge also dynamic dataflow actors. To support these claims, results of experiments on several processing platforms and application examples ranging from telecommunications to video compression are reported.

Data Intensive Computing: From Modeling to Implementation

Data intensive computing encompasses applications that mostly perform data processing in regular patterns. Traditionally, such applications have been found, e.g., in image processing, audio processing, telecommunications and radar signal processing. With the immense growth of the mobile consumer electronics market, data intensive computing is present in billions of devices. In contrast to general-purpose computing, the regularity of data intensive computing enables intelligent design choices to be made in specification, modeling, design space exploration, software design, compilation and hardware design. However, unlike classic signal processing, contemporary data intensive applications, such as a H.265 video decoding or cognitive radio radio systems cannot be described with fully static representations. This dynamic nature of contemporary data intensive applications has its implications to all layers of system design, from higher-level software to hardware implementation. This special issue covers topics from the whole spectrum of design aspects for data intensive computing. Included are three articles that address dataflow specification and analysis of applications, four articles that address programmable processing hardware for data intensive applications and one publication that deals with both software and hardware design aspects. Article Parameterized Sets of Dataflow Modes and Their Application to Implementation of Cognitive Radio Systems (doi:10.1007/s11265-014-0938-4) presents a novel dataflow modeling technique named parameterized sets of modes (PSM) that addresses the important issue of modeling reconfigurable data intensive systems. After presenting a formal definition of the new concept, a cognitive radio application example is presented. Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs (doi:10.1007/ s11265-014-0952-6) is an article that concentrates on the memory usage analysis and optimization of applications that target MPSoC platforms. The application is modeled with the well-known Synchronous Dataflow formalism, based on which the memory usage analysis and optimization is performed. Experiments are performed with several data intensive applications on Intel and Texas Instruments DSP multicores. The paperModeling Resolution of Resources Contention in Synchronous Data Flow Graphs (doi:10.1007/s11265-0140923-y) addresses interprocessor communication contention on multicore platforms. The proposed approach uses Synchronous Dataflow graphs to model applications and to perform the resource contention analysis. Experiments consist from random application graphs to well-known data intensive applications, such as video and audio codecs. When going towards the hardware implementation level, issues such as processor instruction-set architectures suitable for data intensive computing become of interest. To this end, Code Density and Energy Efficiency of Exposed Datapath Architectures (doi:10.1007/s11265-014-0924-x) gives an overview of an instruction-set design direction where nontraditional aspects of the datapath are exposed to the control of the programmer in order to improve energy efficiency and instruction-level parallelism. The article looks at several proposed variations of the so called exposed datapath architectures with focus on their instruction word width overheads. A Low Energy Wide SIMD Architecture with Explicit Datapath (doi:10.1007/s11265-014-0950-8) proposes a dataoriented processor architecture which exposes the bypass P. Jaaskelainen (*) Tampere University of Technology, Tampere, Finland e-mail: pekka.jaaskelainen@tut.fi

Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems

As the number of processors in a chip increases and more functions are integrated, the system status will change dynamically due to various factors such as the workload variation, QoS requirement, and unexpected component failure. A typical method to deal with the dynamics of the system is to decide the mapping decision at runtime, based on the local information of the system status. It is very challenging to guarantee any real-time performance of a certain application in such a dynamically varying system. To solve this problem, we propose a hybrid specification of dataflow and FSM models to specify the dynamic behavior of a system distinguishing inter- and intra-application dynamism. At the top level, each application is specified by a dataflow task and the dynamic behavior is modeled as a control task that supervises the execution of applications. Inside a dataflow task, we specify the dynamic behavior using a similar way as FSM-based SADF in which an application is specified by a synchronous dataflow graph for each mode of operation. It enables us to perform compile-time scheduling of each graph to maximize the throughput varying the number of allocated processors, and store the scheduling information. When a change in system state is detected at runtime, the number of allocated processors to the active tasks is determined dynamically utilizing the stored scheduling information of those tasks in order to meet the real-time requirements. The proposed technique is implemented in the HOPES design environment. Through preliminary experiments with a simple smartphone example, we show the viability of the proposed methodology.

Eddy, a formal language for specifying and analyzing data flow specifications for conflicting privacy requirements

Increasingly, companies use multi-source data to operate new information systems, such as social networking, e-commerce, and location-based services. These systems leverage complex, multi-stakeholder data supply chains in which each stakeholder (e.g., users, developers, companies, and government) must manage privacy and security requirements that cover their practices. US regulator and European regulator expect companies to ensure consistency between their privacy policies and their data practices, including restrictions on what data may be collected, how it may be used, to whom it may be transferred, and for what purposes. To help developers check consistency, we identified a strict subset of commonly found privacy requirements and we developed a methodology to map these requirements from natural language text to a formal language in description logic, called Eddy. Using this language, developers can detect conflicting privacy requirements within a policy and enable the tracing of data flows within these policies. We derived our methodology from an exploratory case study of the Facebook platform policy and an extended case study using privacy policies from Zynga and AOL Advertising. In this paper, we report results from multiple analysts in a literal replication study, which includes a refined methodology and set of heuristics that we used to extract privacy requirements from policy texts. In addition to providing the method, we report results from performing automated conflict detection within the Facebook, Zynga, and AOL privacy specifications, and results from a computer simulation that demonstrates the scalability of our formal language toolset to specifications of reasonable size.

Throughput-memory footprint trade-off in synthesis of streaming software on embedded multiprocessors

We study the trade-off between throughput and memory footprint of embedded software that is synthesized from acyclic static dataflow (task graph) specifications targeting distributed memory multiprocessors. We identify iteration overlapping as a knob in the synthesis process by which one can trade application throughput for its memory requirement. Given an initial processor assignment and non-overlapped task schedule, we formally present underlying properties of the problem, such as constraints on a valid iteration overlapping, maximum possible throughput, and minimum memory footprint. Moreover, we develop an effective algorithm for generation of a rich set of design points that provide a range of trade-off options. Experimental results on a number of applications and architectures validate the effectiveness of our approach.

Methods to explore design space for MPEG RMC codec specifications

The recent MPEG Reconfigurable Media Coding (RMC) standard aims at defining media processing specifications (e.g. video codecs) in a form that abstracts from the implementation platform, but at the same time is an appropriate starting point for implementation on specific targets. To this end, the RMC framework has standardized both an asynchronous dataflow model of computation and an associated specification language. Either are providing the formalism and the theoretical foundation for multimedia specifications. Even though these specifications are abstract and platform-independent the new approach of developing implementations from such initial specifications presents obvious advantages over the approaches based on classical sequential specifications. The advantages appear particularly appealing when targeting the current and emerging homogeneous and heterogeneous manycore or multicore processing platforms. These highly parallel computing machines are gradually replacing single-core processors, particularly when the system design aims at reducing power dissipation or at increasing throughput. However, a straightforward mapping of an abstract dataflow specification onto a concurrent and heterogeneous platform does often not produce an efficient result. Before an abstract specification can be translated into an efficient implementation in software and hardware, the dataflow networks need to be partitioned and then mapped to individual processing elements. Moreover, system performance requirements need to be accounted for in the design optimization process. This paper discusses the state of the art of the combinatorial problems that need to be faced at this design space exploration step. Some recent developments and experimental results for image and video coding applications are illustrated. Both well-known and novel heuristics for problems such as mapping, scheduling and buffer minimization are investigated in the specific context of exploring the design space of dataflow program implementations.

The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms

Dataflow specifications are suitable to describe both signal processing applications and the relative specialized hardware architectures, fostering the hardware---software development gap closure. They can be exploited for the development of automatic tools aimed at the integration of multiple applications on the same coarse-grained computational substrate. In this paper, the multi-dataflow composer (MDC) tool, a novel automatic platform builder exploiting dataflow specifications for the creation of run-time reconfigurable multi-application systems, is presented and evaluated. In order to prove the effectiveness of the adopted approach, a coprocessor for still image and video processing acceleration has been assembled and implemented on both FPGA and 90 nm ASIC technology. 60 % of savings for both area occupancy and power consumption can be achieved with the MDC generated coprocessor compared to an equivalent non-reconfigurable design, without performance losses. Thanks to the generality of high-level dataflow specification approach, this tool can be successfully applied in different application domains.

From dataflow specification to multiprocessor partitioned time-triggered real-time implementation

Our objective is to facilitate the development of complex time-triggered systems by automating the allocation and scheduling steps. We show that full automation is possible while taking into account the elements of complexity needed by a complex embedded control system. More precisely, we consider deterministic functional specifications provided (as often in an industrial setting) by means of synchronous data-flow models with multiple modes and multiple relative periods. We first extend this functional model with an original real-time characterization that takes advantage of our time-triggered framework to provide a simpler representation of complex end-to-end flow requirements. We also extend our specifications with additional non-functional properties specifying partitioning, allocation, and preemptability constraints. Then, we provide novel algorithms for the off-line scheduling of these extended specifications onto partitioned time-triggered architectures a la ARINC 653. The main originality of our work is that it takes into account at the same time multiple complexity elements: various types of non-functional properties (real-time, partitioning, allocation, preemptability) and functional specifications with conditional execution and multiple modes. Allocation of time slots/windows to partitions can be fully or partially provided, or synthesized by our tool. Our algorithms allow the automatic allocation and scheduling onto multi-processor (distributed) systems with a global time base, taking into account communication costs. We demonstrate our technique on a model of space flight software system with strong real-time determinism requirements.

FORMLESS

Variants of dataflow specification models are widely used to synthesize streaming applications for distributed-memory parallel processors. We argue that current practice of specifying streaming applications using rigid dataflow models, implicitly prohibits a number of platform oriented optimizations and hence limits portability and scalability with respect to number of processors. We motivate Functionally-cOnsistent stRucturally-MalLEabe Streaming Specification , dubbed FORMLESS, which refers to raising the abstraction level beyond fixed-structure dataflow to address its portability and scalability limitations. To demonstrate the potential of the idea, we develop a design space exploration scheme to customize the application specification to better fit the target platform. Experiments with several common streaming case studies demonstrate improved portability and scalability over conventional dataflow specification models, and confirm the effectiveness of our approach.

A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification

The design space exploration (DSE) problem addressed in this paper is to find out Multi-Processor System-on-Chip architectures for a given multi-task signal processing application aiming to minimize the system cost while satisfying the real-time constraints. It involves the following three sub-problems: selecting processing elements, mapping an application to the processing elements, and determining the communication architecture. The proposed approach consists of two inner design loops: one is a cosynthesis loop that determines the selection of PEs and the mapping of a given application to the PEs, and the other is a communication architecture synthesis loop to find the hierarchical shared bus architecture. We specify an application with a synchronous data flow (SDF) model of computation that has well-matched semantics with the algorithmic function flow in DSP applications. To solve the problem, we need to compare the estimated performance of design points and choose the best ones. The common method of simulation-based performance estimation is too time-consuming to explore the wide design space. Thanks to the analytical properties of the SDF model, the performance estimation can be done without HW/SW cosimulation in both loops. A global feedback from the communication architecture synthesis step to the cosynthesis step forms the proposed DSE framework. We use a real-life application, 4-channel Digital Video Recorder (DVR) that is a multi-task example, as well as randomly generated graphs to show the viability of the proposed approach.

The Data Flow Problem in Learning Design

A teaching-learning process formalized through the IMS-Learning Design specification (IMS-LD) comprises a sequence of learning activities (learning flow) as well as a sequence of artifacts between tools or services (data flow) used to support the learning activities. According to the literature, the collaborative learning flow specification has been successfully achieved; however the automation of the collaborative data flow is still an open issue in IMS-LD. Nevertheless, no case studies have been reported in the literature in order to show with real data why the automation of the data flow is an important issue in Learning Design (LD). In this paper an authentic case study which is significative and relevant to the problem is analyzed. Supported with real data, several findings related to the data flow problem in collaborative learning emerged: data management is error-prone for the users; data flow specification is error-prone for the course designer; users suffer an additional cognitive load during the data management; the course designer suffers an additional cognitive load during the data flow specification; and the need to include instance-level data flow specification within the learning design has also been identified. Furthermore, these findings also help us to understand the relevance of the problem: a data flow approach which is error-prone for both the users and the course designer may potentially affect the accomplishment of the users’ learning objectives; and a learning design which merge declarative-level learning flow with instance-level data flow affects the reusability of the whole unit of learning (UoL). Based on the relation among these findings and literature, three dimensions of the IMS-LD data flow problem have been identified: the data flow automation problem already reported in the literature, which is related to the user’s data flow management issue; the data flow consistency problem, which is related to the issue of matching the different parts that comprise the data flow specification; and the UoL reuse problem, which is related to the instance-level collaborative data flow specification issue. Furthermore, these dimensions also help us to determine the necessary requirements in order to tackle these problems. Since IMS-LD fails to specify the data flow in collaborative learning, we propose a separation of the data flow from the learning flow. For this purpose, a standard workflow language such as BPEL is used and a unit of data flow (UoDF), which is just a business process archive (BPR) understandable by a BPEL-compliant engine is created. Then, the learning design is specified in a unit of learning flow (UoLF), which is actually a UoL understandable by an IMS-LD compliant engine that follows the best practices in collaborative data flow specification, which means not specifying the data flow at all. Finally, for coordination of both engines, a coordination model has been developed and a prototype is currently under test and evaluation. Future work includes evaluation of more case studies in order to validate the proposal solution, and identify limitations and drawbacks. Interestingly is that our proposal which is based on a composition-based approach may be thought as the in-between approach that will provide a framework for future integration of LD and workflow streams.

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

Beyond single-appearance schedules

Synthesis of digital signal-processing (DSP) software from dataflow-based formal models is an effective approach for tackling the complexity of modern DSP applications. In this paper, an efficient method is proposed for applying subroutine call instantiation of module functionality when synthesizing embedded software from a dataflow specification. The technique is based on a novel recursive decomposition of subgraphs in a cluster hierarchy that is optimized for low buffer size. Applying this technique, one can achieve significantly lower buffer sizes than what is available for minimum code size inlined schedules, which have been the emphasis of prior work on software synthesis. Furthermore, it is guaranteed that the number of procedure calls in the synthesized program is polynomially bounded in the size of the input dataflow graph, even though the number of module invocations may increase exponentially. This recursive decomposition approach provides an efficient means for integrating subroutine-based module instantiation into the design space of DSP software synthesis. The experimental results demonstrate a significant improvement in buffer cost, especially for more irregular multirate DSP applications, with moderate code and execution time overhead.