Dataflow Programming Research Articles

DF‐DTM: Dynamic Task Memoization and reuse in dataflow

SummaryInstruction Reuse is a technique adopted in Von Neumann architectures that improves performance by avoiding redundant execution of instructions when the result to be produced can be obtained by searching an input/output memoization table for such instruction. Trace reuse can be applied to traces of instructions in a similar fashion. However, those techniques are yet to be studied in the context of the Dataflow model, which has been gaining traction in the high performance computing community due to its inherent parallelism. Dataflow programs are represented by directed graphs where nodes are instructions or tasks and edges denote data dependencies between tasks. This work presents Dataflow Dynamic Task Memoization (DF‐DTM), a technique that allows the reuse of both nodes and subgraphs in dataflow, which are analogous to instructions and traces, respectively. The potential of DF‐DTM is evaluated by a series of experiments that analyze the behavior of redundant tasks in five relevant benchmarks, where up to 99.70% of the instantiated tasks could be reused. Moreover, this paper evaluates how reuse rates can be affected by limiting subgraph size, memoization table size, task granularity, and problem size, showing that DF‐DTM can yield good reuse rates in more realistic environments.

Fault tolerant functional reactive programming (functional pearl)

Highly critical application domains, like medicine and aerospace, require the use of strict design, implementation and validation techniques. Functional languages have been used in these domains to develop synchronous dataflow programming languages for reactive systems. Causal stream functions and Functional Reactive Programming capture the essence of those languages in a way that is both elegant and robust. To guarantee that critical systems can operate under high stress over long periods of time, these applications require clear specifications of possible faults and hazards, and how they are being handled. Modeling failure is straightforward in functional languages, and many Functional Reactive abstractions incorporate support for failure or termination. However, handling unknown types of faults , and incorporating fault tolerance into Functional Reactive Programming, requires a different construction and remains an open problem. This work presents extensions to an existing functional reactive abstraction to facilitate tagging reactive transformations with hazard tags or confidence levels. We present a prototype framework to quantify the reliability of a reactive construction, by means of numeric factors or probability distributions, and demonstrate how to aid the design of fault-tolerant systems, by constraining the allowed reliability to required boundaries. By applying type-level programming, we show that it is possible to improve static analysis and have compile-time guarantees of key aspects of fault tolerance. Our approach is powerful enough to be used in systems with realistic complexity, and flexible enough to be used to guide their analysis and design, to test system properties, to verify fault tolerance properties, to perform runtime monitoring, to implement fault tolerance during execution and to address faults during runtime. We present implementations in Haskell and in Idris.

Execution Trace Graph of Dataflow Process Networks

The paper introduces and specifies a formalism that provides complete representations of dataflow process network (DPN) program executions, by means of directed acyclic graphs. Such graphs, also known as execution trace graphs (ETG), are composed of nodes representing each action firing and by directed arcs representing the dataflow program execution constraints between two action firings. Action firings are atomic operations that encompass the algorithmic part of the action executions applied to both, the input data and the actor state variables. The paper describes how an ETG can be effectively derived from a dataflow program, specifies the type of dependencies that need to be included, and the processing that need to be applied so that an ETG become capable of representing all the admissible trajectories that dynamic dataflow programs can execute. The paper also describes how some characteristics of the ETG, related to specific implementations of the dataflow program, can be evaluated by means of high-level and architecture-independent executions of the program. Furthermore, some examples are provided showing how the analysis of the ETGs can support efficient explorations, reductions, and optimizations of the design space, providing results in terms of design alternatives, without requiring any partial implementation or reduction of the expressiveness of the original DPN dataflow program.

A Hardware/Software Stack for Heterogeneous Systems

Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.

An FPGA-friendly CABAC-encoding architecture with dataflow modelling programming

ABSTRACTVideo compression standards play an important role in video encoding, transmitting and decoding. To exploit the similarities or commonality among standards, a Reconfigurable Video Coding framework is developed in MPEG by employing a dataflow modelling method to modulate the basic configuration components of encoders or decoders. However, the entropy coding for bitstream generating and parsing during the configuration process is very complex, especially when employing the Context Adaptive Based Arithmetic Coding (CABAC). This paper proposes an optimized ‘Producer–Consumer’ architecture for CABAC by dataflow modelling. To achieve high-throughput and low-resource consumption, the buffer accessing speed and buffer size in the architecture is analysed and refined. The proposed CABAC is implemented by dataflow language Cal and is synthesized to FPGA. Results show that it can process 3.5 bins/cycle with a 10-byte buffer consumption at a 120 MHz working frequency. It is sufficient for real-time encoding of H.265/HEVC at level 6.2 main tier.

Evaluation of dataflow programming models for electronic structure theory

SummaryDataflow programming models have been growing in popularity as a means to deliver a good balance between performance and portability in the post‐petascale era. In this paper, we evaluate different dataflow programming models for electronic structure methods and compare them in terms of programmability, resource utilization, and scalability. In particular, we evaluate two programming paradigms for expressing scientific applications in a dataflow form: (1) explicit dataflow, where the dataflow is specified explicitly by the developer, and (2) implicit dataflow, where a task scheduling runtime derives the dataflow using per‐task data‐access information embedded in a serial program. We discuss our findings and present a thorough experimental analysis using methods from the NWChem quantum chemistry application as our case study, and OpenMP, StarPU, and PaRSEC as the task‐based runtimes that enable the different forms of dataflow execution. Furthermore, we derive an abstract model to explore the limits of the different dataflow programming paradigms.

CS::APEX: A Framework for Algorithm Prototyping and Experimentation with Robotic Systems

Robotic systems differ drastically in their sensory capabilities, their computational power and their designated tasks. For efficient algorithm development, however, we need to have a common modeling framework that enables us to generalize and re-use existing solutions. A modular approach, which is coherent across different platforms, also allows faster prototyping of new systems, given that existing functionality can be reused from already implemented modules. In this paper we develop a modeling framework based on data flow graphs that achieves the following goal: We first merge synchronous data flow and reactive programming into hybrid flow graphs, where we explicitly model synchronous and asynchronous data flow. Then we transfer concepts from finite-state machines to achieve a coherent framework which we call Activity Flow Graphs. The flow of activity enables us to model high level states directly in the data flow graph. The result is a single computation graph that can express both perception and high level control aspects of any robotic system. This theoretical foundation is the core of our open-source software framework CS::APEX, which allows the creation, manipulation and evaluation of Activity Flow Graphs and enables rapid prototyping and experimentation and can be used with any robot supporting the Robot Operating System (ROS). We then demonstrate the framework with two high level models for a fetch-and-delivery robot and a person following robot.

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures—and, consequently, exploration of the design space—by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4 × improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5–13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of hand-written implementations.

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

The implementation and optimization of dynamic dataflow programs on multi/many-core platforms require solving a very difficult problem: how to partition and schedule the processing elements and dimension their interconnecting buffers according to given optimization functions in terms of throughput, memory usage, and energy consumption. This problem is NP-hard even for two cores. Thus, finding a close-to-optimal solution consists of exploring the design space by appropriate heuristics identifying those design points that maximize or minimize the desired (multiple) objective functions subject to a set of constraints. In general, exploring the design space efficiently is a challenging task due to the massive number of admissible design points. Efficient estimation methodologies are necessary to support an effective search of the design space by reducing to a minimum the cost and the number of measurements on the physical platform. This paper presents a new methodology that provides high-precision estimations of dynamic dataflow programs performances on multi/many-core platforms for any set of design configurations. The estimations rely on the execution trace post-processing obtained by a single profiled execution of the program. Furthermore, the paper describes the estimation methodology, implementation tools, and the type of information that is obtained from many/multi-core dataflow executions and used to drive the optimization heuristics. The results confirm a high level of accuracy achieved on different types of platforms and the effectiveness of the illustrated design space exploration methodology.

Control and data acquisition system for SCR-1 Stellarator

The design and implementation of a small-size modular stellarator’s (SCR-1) control and data acquisition system is introduced and discussed in this article. The described development includes the validation and integration of vacuum pumping, gas injection, Electron Cyclotron Heating (ECH), diagnostics, and magnetic confinement systems of the SCR-1.The control system was implemented on a National Instruments® PXIe® platform. By data flow programming, it was possible to develop different algorithms for the simultaneous execution of four threads during the plasma discharge sequence (device safety, gas injection, data acquisition and plasma discharge), where the primary goal is to implement a robust and secure system considering the integrity and safety of the SCR-1 work team and the hardware involved. Through the implementation of this control and data acquisition system, it was possible to perform the first plasma discharge and, therefore, obtain first data of device operation.

HitFlow: A Dataflow Programming Model for Hybrid Distributed- and Shared-Memory Systems

Dataflow programming consists in developing a program by describing its sequential stages and the interactions between them. The runtime systems supporting this kind of programming are responsible for exploiting the parallelism by concurrently executing the different stages as soon as their dependencies are met. In this paper we introduce a new parallel programming model and framework based on the dataflow paradigm. It presents a new combination of features that allows to easily map programs to shared or distributed memory, exploiting data locality and affinity to obtain the same performance than optimized coarse-grain MPI programs. These features include: It is a unique one-tier model that supports hybrid shared- and distributed-memory systems with the same abstractions; it can express activities arbitrarily linked, including non-nested cycles; it uses internally a distributed work-stealing mechanism to allow Multiple-Producer/Multiple-Consumer configurations; and it has a runtime mechanism for the reconfiguration of the dependences and communication channels which also allows the creation of task-to-task data affinities. We present an evaluation using examples of different classes of applications. Experimental results show that programs generated using this framework deliver good performance in hybrid distributed- and shared-memory environments, with a similar development effort as other dataflow programming models oriented to shared-memory.

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

The increasing number of cores in System on Chips (SoC) has introduced challenges in software parallelization. As an answer to this, the dataflow programming model offers a concurrent and reusability promoting approach for describing applications. In this work, a runtime for executing Dataflow Process Networks (DPN) on multicore platforms is proposed. The main difference between this work and existing methods is letting the operating system perform Central processing unit (CPU) load-balancing freely, instead of limiting thread migration between processing cores through CPU affinity. The proposed runtime is benchmarked on desktop and server multicore platforms using five different applications from video coding and telecommunication domains. The results show that the proposed method offers significant improvements over the state-of-art, in terms of performance and reliability.

Modeling and prototyping of biometric systems using dataflow programming

The development of biometric systems is one of the labor-intensive processes. Therefore, the creation and analysis of approaches and techniques is an urgent task at present. This article presents a technique of modeling and prototyping biometric systems based on dataflow programming. The technique includes three main stages: the development of functional blocks, the creation of a dataflow graph and the generation of a prototype. A specially developed software modeling environment that implements this technique is described. As an example of the use of this technique, an example of the implementation of the iris localization subsystem is demonstrated. A variant of modification of dataflow programming is suggested to solve the problem related to the undefined order of block activation. The main advantage of the presented technique is the ability to visually display and design the model of the biometric system, the rapid creation of a working prototype and the reuse of the previously developed functional blocks.

Study of voice data communication using network streams on dataflow programming

In this paper, we implement a voice data communications between sender and receiver through Wi-Fi. The system was designed and implemented using network stream protocol which was developed by National Instruments on Lab-VIEW between two devices. The device which acts as the sender was My-RIO board and the receiver device was Personal Computer. The voice data communication system was tested by observing the effect of various buffer sizes on the throughput, latency and CPU usage. The result showed that the larger the buffer size being used, the throughput values were also getting bigger. However, particular buffer size made the throughput became saturated. The change on the buffer size also directly affects CPU usage. It seemed that the buffer size did not affect latency significantly. It showed that the latency was stable with an average of 13 milliseconds on voice data transmission.

Implementation of dataflow programming based Fuzzy Logic algorithm for gas concentration index in around of Sidoarjo mudflow, Indonesia

Sidoarjo mudflow or known as Lapindo mudflow erupted since 2006. The Sidoarjo mudflow is located in Sidoarjo City, East Java, Indonesia. The mudflow-affected area has high air pollution level and high health risk. Therefore, in this paper was implemented a system that can categorize the level of air pollution into several categories. The air quality index can be categorized using fuzzy logic algorithm based on the concentration of air pollutant parameters in the mudflow-affected area. Furthermore, Dataflow programming is used to process the fuzzy logic algorithm. Based on the result, the measurement accuracy of the air quality index in the mudflow-affected area has an accuracy rate of 93.92% in Siring Barat, 93.34% in Mindi, and 95.96% in Jatirejo. The methane concentration is passes the standard quality even though the air quality index is safe. Hence, the area is indicated into Hazardous level. In addition, Mindi has highest and stable methane concentration. It means that Mindi has high-risk air pollution.

Exogenous Coordination for Building Fog-Based Cyber Physical Social Computing and Networking Systems

With the proliferation of smart embedded devices, cyber physical social computing and networking systems (CPSCN) are emerging as a next generation of social networks. Unlike traditional social networks that run on cloud-based infrastructure, CPSCN systems usually depend on a large number of distributed, heterogeneous devices, such as mobile phones, smart vehicles, or network access points. These computing resources, which are often referred to as fog computing systems, provide a gateway to the physical world, and thus offer new possibilities for social applications. Unfortunately, building CPSCN systems that leverage fog computing infrastructure is not straightforward. Significant challenges arise from the large scale distribution of computing resources over a wide area, and the dynamic nature of multiple, possibly mobile, hosts. In this paper, we extend our previous work on a distributed dataflow programming model and propose an application platform for realizing CPSCN systems. A key aspect of our work is the development of an exogenous coordination model, which exhibits a separation of concern between computation and communication activities, and helps resolve some of the challenges brought about by the dynamic and large scale nature of CPSCN systems.

Data-Flow Programming Paradigm for High Level Synthesis Improvement

Data-Flow Programming Paradigm for High Level Synthesis Improvement

Output nondeterminism detection for programming models combining dataflow with shared memory

Abstract Implementing highly concurrent programs can be challenging because programmers can easily introduce unintended nondeterminism, which has the potential to affect the program output. We propose and implement a technique for detecting unintended nondeterminism in applications developed on shared memory systems with dataflow execution model. Such nondeterminism bugs may be caused by missing or incorrect ordering of task dependencies that are used for ensuring certain ordering of tasks. The proposed method is based on the formulation of happens-before relation on tasks executions in a dataflow dependency graph. Its implementation is composed of two main phases; log recording and detection. For recording the necessary information from the execution, the tool instruments the dataflow framework and the applications, on top of the LLVM compiler infrastructure. Later it processes the collected log and reports on the found output nondeterminism in the execution. The tool can integrate well with the development cycle to provide the programmer with a testing framework against possible nondeterminism bugs. To demonstrate its effectiveness, we study a set of benchmark applications written in Atomic DataFlow programming model and report on real nondeterminism bugs in them.

Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs

Dataflow programming has received increasing attention in the age of multicore and heterogeneous computing. Modular and concurrent dataflow program descriptions enable highly automated approaches for design space exploration, optimization and deployment of applications. A great advance in dataflow programming has been the recent introduction of the RVC-CAL language. Having been standardized by the ISO, the RVC-CAL dataflow language provides a solid basis for the development of tools, design methodologies and design flows. This paper proposes a novel design flow for mapping RVC-CAL dataflow programs to parallel and heterogeneous execution platforms. Through the proposed design flow the programmer can describe an application in the RVC-CAL language and map it to multi- and many-core platforms, as well as GPUs, for efficient execution. The functionality and efficiency of the proposed approach is demonstrated by a parallel implementation of a video processing application and a run-time reconfigurable filter for telecommunications. Experiments are performed on GPU and multicore platforms with up to 16 cores, and the results show that for high-performance applications the proposed design flow provides up to 4 × higher throughput than the state-of-the-art approach in multicore execution of RVC-CAL programs.

Hardware design methodology using lightweight dataflow and its integration with low power techniques

Abstract Dataflow models of computation are capable of providing high-level descriptions for hardware and software components and systems, facilitating efficient processes for system-level design. The modularity and parallelism of dataflow representations make them suitable for key aspects of design exploration and optimization, such as efficient scheduling, task synchronization, memory and power management. The lightweight dataflow (LWDF) programming methodology provides an abstract programming model that supports dataflow-based design of signal processing hardware and software components and systems. Due to its formulation in terms of abstract application programming interfaces, the LWDF methodology can be integrated with a wide variety of simulation- and implementation-oriented languages, and can be targeted across different platforms, which allows engineers to integrate dataflow modeling approaches relatively easily into existing design processes. Previous work on LWDF techniques has emphasized their application to DSP software implementation (e.g., through integration with C and CUDA). In this paper, we efficiently integrate the LWDF methodology with hardware description languages (HDLs), and we apply this HDL-integrated form of the methodology to develop efficient methods for low power DSP hardware implementation. The effectiveness of the proposed LWDF-based hardware design methodology is demonstrated through a case study of a deep neural network application for vehicle classification.