Data Switching Activity Research Articles

Data branch sharing dual‐edge explicit‐pulsed level converting flip‐flops

AbstractVariable supply clustered voltage scaling (VS‐CVS) is an effective way to decrease power consumption without compromising performance. One of the major challenges in VS‐CVS design is that level converting flip‐flops (LCFFs) not only need to have low power consumption but also high performance. In this paper, we propose two new structures of LCFF: the data branch sharing LCFF based on conditional charging (DBS‐LCFFCC) and the data branch sharing LCFF based on precharging (DBS‐LCFFP). The new structures adopt a data branch sharing scheme to improve the speed of the circuit as well as to reduce the number of transistors. Based on simulation results using HSPICE with PTM 32‐nm CMOS technology, the proposed LCFFs show an improvement of 19.2–67.2% and 41.6–76.3% in power‐delay‐product (PDP) at 50% data switching activity, respectively, compared to other advanced LCFFs.

High speed ultra-low-lower lulse-triggered JLFET Flip-Flop

Power efficiency and enhancing the speed are two major challenges of traditional D-Flip-Flops (D-FF) for designing energy-efficient IOT (internet of thing) devices. Therefore, the main objective of this research article is to design low power high speed D-FF circuits using emerging nanoscale devices. Hence, the first time, in this paper, a pulse-triggered Junctionless D-Flip-Flop (JLFET D-FF) circuit is presented using 15 nm technology, targeting both power budget and high performance concerns. Here, the D-FF circuit uses a signal feedthrough approach to minimize transition duration when output switches from 0 to 1, which requires only a single JLFET structure. Further, to minimize the delay time for the 1 to 0 transition, the discharging path is optimized by employing only two JLFETs. The novel JLFET D-FF circuit is simulated in the Cadence virtuoso simulator using the Verilog-A model. The simulated results have shown that the average power consumption and delay of the proposed circuit are significantly improved as compared to the earlier reported work. The average power consumption in JLFET D-FF for 25% data switching activity is improved by approximately 56% and 64% than ULPFF and SFT-FF, respectively. Further, the power delay performance (PDP) of JLFET D-FF is improved by 96% and 97% at the same data switching activity as compared to ULPFF and SFT-FF, respectively. The performance of the novel D-FF circuit is measured by considering D to Q delay as key parameter which is improved by 77% and 77.5% than ULPFF and SFT-FF, respectively. The simulation results of this work can give insights into the in-circuit behavior of modern semiconductor devices.

Low power design of explicit‐pulsed dual‐edge‐triggered level‐converting flip‐flop based on carbon nanotubes field‐effect transistors

Power consumption and performance are the two main concerns in designing pulse-triggered level-converting flip-flops (LCFF). In this letter, through the research on the level conversion circuits, an explicit-pulsed dual-edge triggered LCFF based on the carbon nanotubes field-effect transistors (CNTFETs) is proposed by using the multi-source voltage technology. The proposed flip-flop increases the speed by reducing the number of transistors in the charge/discharge path. The characteristics of the CNTFETs are used to obtain transistors with different threshold voltages by changing the chiral vector to optimize the circuit structure and further reduce the power consumption. In addition, the power consumption is further reduced due to the small on-current of the CNTFETs. The proposed novel structure is simulated in HSPICE using the Stanford model. Simulation results indicate that our proposed flip-flop reduces 62.9% to 72.4% of power consumption and 73.6% to 89.1% of delay in comparison with other flip-flops proposed in the references at 50% data switching activity.

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design.

A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.

Automatic Generation of Peak-Power Traffic for Networks-on-Chip

Early estimation of the peak power consumption of a system under development is crucial in assessing the design’s thermal profile and reliability, and in benchmarking the chip-level power management features. In this paper, we present a high-level systematic methodology for generating the appropriate traffic patterns that trigger the peak power consumption in a network-on-chip (NoC), irrespective of the latter’s structural and functional properties. The generation of peak-power traffic is performed by solving a novel optimization problem based on integer linear programming, which models the traffic that can realistically flow in the network, thus avoiding any fake and pessimistic scenarios. This formulation can handle arbitrary network configurations and routing algorithms, including heterogeneous network topologies with multiple link widths and voltage/clock domains. The proposed technique maximizes both the network utilization and the data switching activity, thereby causing, on average, ${4 \times }$ higher power consumption than synthetic traffic patterns with random behavior. Most importantly, the proposed method reveals the realistic ceiling of the NoC’s peak power consumption, by reporting significantly lower peak power ( ${3\times }$ less), as compared to fake worst-case scenarios that can never, in fact, occur during the NoC’s normal operation.

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme condi- tionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

Design of flip‐flops with clock‐gating and pull‐up control scheme for power‐constrained and speed‐insensitive applications

In this study, a novel power efficient implicit pulsed-triggered flip-flop with embedded clock-gating and pull-up control scheme (IPFF-CGPC) is proposed. By applying an XOR-based clock-gating scheme in the pulse generating stage, which conditionally disables the inverter chain when the input keeps unchanged, IPFF-CGPC is able to gain low power efficiency by eliminating redundant transitions of internal nodes. Meanwhile, a pull-up control scheme is applied to enhance the discharging path and save short-circuit power when D makes ‘0’–‘1’ transition. To further improve the robustness of the proposed design, the XOR-based comparator in the clock-gating scheme is replaced by a transmission gate-based comparator, which results in an enhanced version (IPFF-ECGPC). Based on the SMIC 65 nm technology, extensive post-layout simulation results show that IPFF-CGPC exhibits excellent power characteristic with a reduction of 32.06–85.89% against its rival designs at 10% data switching activity. Due to its power efficiency, its power-delay product (PDP) gains an improvement of up to 73.94% in the same condition. Moreover, IPFF-ECGPC also enjoys outstanding total-power and PDP efficiency at 10% data switching activity. Therefore, the proposed designs are suitable for power-constrained applications in very-large-scale integration designs which are speed-insensitive.

Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption.

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

Ultralow-power high-speed flip-flop based on multimode FinFETs

In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flipflop (S2CFF) based on high-performance fin-type field-effect transistors (FinFETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate (SG-mode) FinFET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power (LP-mode) FinFET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed. However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input ‘0’, which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode) FinFET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinFET flip-flop.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

A novel low power and high speed double edge explicit pulse triggered level converter flip‐flop

SummaryOne of the effective ways to reduce power consumption is using clustered voltage scaling technique. The level converter flip‐flop is needed to control static current when the block with Low Supply Voltage (VDDL) drives the block with High Supply Voltage (VDDH). One of the big challenges of design is that level converter flip‐flop has low power and high speed. In this paper, pulse triggered level converter flip‐flop and double edge pulse generator were proposed. This level converter flip‐flop used conditional data mapping technique for reducing power consumption. An explicit double edge pulse generator could be shared among several level converter flip‐flops so that power consumption would be reduced. Also, the number of stack transistor was reduced in the discharging path that causes delay decrease. The simulation results showed that the proposed flip‐flop reduced 20% of power consumption and 17% of delay in comparison with other flip‐flops at 50% data switching activity. Copyright © 2013 John Wiley & Sons, Ltd.

High-performance and low-power conditional discharge flip-flop

In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.