Data Rate Of IEEE Research Articles

A New Automotive VLC System Using Optical Communication Image Sensor

As a new technology for next-generation vehicle-to-everything (V2X) communication, visible-light communication (VLC) using light-emitting diode (LED) transmitters and camera receivers has been energetically studied. Toward the future in which vehicles are connected anytime and anywhere by optical signals, the cutting-edge camera receiver employing a special CMOS image sensor, i.e., the optical communication image sensor (OCI), has been prototyped, and an optical V2V communication system applying this OCI-based camera receiver has already demonstrated 10-Mb/s optical signal transmission between real vehicles during outside driving. In this paper, to reach a transmission performance of 54 Mb/s, which is standardized as the maximum data rate in IEEE 802.11p for V2X communication, a more advanced OCI-based automotive VLC system is described. By introducing optical orthogonal frequency-division multiplexing (optical-OFDM), the new system achieves a more than fivefold higher data rate. Additionally, the frequency response characteristics and circuit noise of the OCI are closely analyzed and taken into account in the signal design. Furthermore, the forward-current limitation of an actual LED is also considered for long operational reliability, i.e., the LED is not operated in overdrive. Bit-error-rate experiments verify a system performance of 45 Mb/s without bit errors and 55 Mb/s with $\text{BER} .

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.