Data Prefetching Research Articles

Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design

A low-complexity depth-reliability-based stereo-matching algorithm and an efficient scanline memory-merging implementation scheme are proposed in this paper. The developed algorithm analyzes the accuracy of disparity results by using simple local window-based methods and preserves reliable information only. A bidirectional depth propagation flow is then adopted to fill the unreliable segments by using reliable information. Moreover, a set of predefined function-specific reliability variables are extracted to further improve depth quality in the occluded and smooth regions, which can reduce 39% bad pixels obtained by applying the basic $7\times 7$ window-based matching. The proposed scanline memory-merging scheme along with data prefetching can lead to 32.7% savings on the scanline memory area and relax the requirements of external frame buffer size and bandwidth. Experimental results show that the implemented stereo-matching hardware has a gate count of 223 k including the scanline memory, and can achieve up to 70 frames/s for $480\times 540$ resolution ( $2\times 2$ downsampling of FullHD side-by-side 3-D format) with 56 disparity levels.

Predictive Prefetching for Parallel Hybrid Storage Systems

In this paper, we present a predictive prefetching mechanism that is based on probability graph approach to perform prefetching between different levels in a parallel hybrid storage system. The fundamental concept of our approach is to invoke parallel hybrid storage system’s parallelism and prefetch data among multiple storage levels (e.g. solid state disks, and hard disk drives) in parallel with the application’s on-demand I/O reading requests. In this study, we show that a predictive prefetching across multiple storage levels is an efficient technique for placing near future needed data blocks in the uppermost levels near the application. Our PPHSS approach extends previous ideas of predictive prefetching in two ways: (1) our approach reduces applications’ execution elapsed time by keeping data blocks that are predicted to be accessed in the near future cached in the uppermost level; (2) we propose a parallel data fetching scheme in which multiple fetching mechanisms (i.e. predictive prefetching and application’s on-demand data requests) can work in parallel; where the first one fetches data blocks among the different levels of the hybrid storage systems (i.e. low-level (slow) to high-level (fast) storage devices) and the other one fetches the data from the storage system to the application. Our PPHSS strategy integrated with the predictive prefetching mechanism significantly reduces overall I/O access time in a hybrid storage system. Finally, we developed a simulator to evaluate the performance of the proposed predictive prefetching scheme in the context of hybrid storage systems. Our results show that our PPHSS can improve system performance by 4% across real-world I/O traces without the need of using large size caches.

Power-efficient prefetching on GPGPUs

The graphics processing unit (GPU) is the most promising candidate platform for achieving faster improvements in peak processing speed, low latency and high performance. The highly programmable and multithreaded nature of GPUs makes them a remarkable candidate for general purpose computing. However, supporting non-graphics computing on graphics processors requires addressing several architectural challenges. In this paper, we focus on improving performance by better hiding long waiting time for transferring data from the slow global memory. Furthermore, we show that the proposed method can reduce power and energy. Reduction in access time to off-chip data has a noticeable role in reducing waiting time and the percentage of unutilized elements. Also, using processing elements in a suitable manner to prefetch data during stall times bridges the memory gap in an energy-efficient manner, and consequently leads to less power and energy consumption. Simulation results show that we can potentially improve instruction per cycle (IPC) up to 24.76 %. Moreover, results show that power, energy and energy efficiency improve by up to 22.47, 24.72 and 36.01 %, respectively.

Research on data pre-deployment in information service flow of digital ocean cloud computing

Data pre-deployment in the HDFS (Hadoop distributed file systems) is more complicated than that in traditional file systems. There are many key issues need to be addressed, such as determining the target location of the data prefetching, the amount of data to be prefetched, the balance between data prefetching services and normal data accesses. Aiming to solve these problems, we employ the characteristics of digital ocean information service flows and propose a deployment scheme which combines input data prefetching with output data oriented storage strategies. The method achieves the parallelism of data preparation and data processing, thereby massively reducing I/O time cost of digital ocean cloud computing platforms when processing multi-source information synergistic tasks. The experimental results show that the scheme has a higher degree of parallelism than traditional Hadoop mechanisms, shortens the waiting time of a running service node, and significantly reduces data access conflicts.

A Caching Strategy for Spatial Queries in Mobile Networks

As a result of the recent developments in mobile terminals such as smartphones and laptop computers, as well as in wireless communication technologies such as GPS, location- based services are coming closer and closer to our daily life. However, the problems associated with the limited resources-such as limited wireless bandwidth, limited battery life, and small memory space-of mobile terminals remain unsolved. Research on cache utilization in mobile terminals, the development of efficient query processing algorithms, and improvement of the index structure in order to support efficient location-based service is geared towards alleviating these problems. In this paper, we propose location- based cache maintenance strategies for wireless broadcast environments in which a mobile client prefetches data that are expected to be used in the near future, and caches and maintains the data at a location close to the client's location. We also propose a hierarchical tree-based privacy approach for supporting anonymous location-based queries in wireless mobile data delivery systems. The results of experiments conducted using our proposed algorithms indicate that they help to reduce communication costs and support rapid spatial query processing.

Integrated Coherence Prediction

Multicore architectures with Network-on-Chips (NoCs) have been widely recognized as the de facto design for the efficient utilization of the continuously increasing density of transistors on a chip. A key challenge in designing such an NoC-based multicore processor is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based protocols, therefore scaling to a large number of cores. However, conventional directory structures add significant indirection delay to cache-to-cache accesses in larger multicore processor. In this article we propose a novel hardware coherence technique, called integrated coherence prediction (ICP). This approach adopts a prediction technique for managing shared data to reduce or eliminate the cache-to-cache delay in coherence accesses. ICP has two unique features that differ from previous coherence prediction techniques. First, ICP introduces a new integrated prediction scheme that combines two kinds of predictors: owner predictor, which predicts the data writers and avoids the indirection through directory, and data predictor, which predicts the access address and prefetches data from remote nodes directly. Second, ICP uses a request replication method to reduce the negative effect of wrong owner prediction operations, thus facilitating overall performance improvement. We present the design and implementation details of the ICP approach. Using detailed full-system simulations, we conclude that the ICP provides a cost-effective solution for designing high-performance multicore processors.

SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors

Dynamic information flow tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities including buffer overflow and format string attacks. Software DIFT implementations suffer from very high performance overheads, while comprehensive hardware implementations add substantial complexity to the microarchitecture, making it unlikely for chip manufacturers to adopt them. In this paper, we propose SIFT (SMT-based DIFT), where a separate thread performing taint propagation and policy checking is executed in a spare context of an SMT processor. The instructions for the checking thread are generated in hardware using self-contained off-the-critical path logic at the commit stage of the pipeline. We investigate several performance optimizations to the base design including: 1) Prefetching of the taint data from shadow memory when the corresponding data is accessed by the primary thread; 2) Optimizing the generation of the taint code to remove unneeded security instructions; and 3) The use of aggregated instructions for collapsing the frequently used groups of security instructions into a single new instruction. Together, these optimizations reduce the performance penalty of SIFT to under 20 percent on SPEC CPU 2006 benchmarks-much lower than the overhead of previously proposed software-based DIFT schemes. We also analyze the energy overhead of SIFT and show it to be very high - 113 percent for SPEC 2006 benchmarks. We then propose several techniques that reduce this overhead to only 23 percent, making SIFT design practical from the energy standpoint. To demonstrate the feasibility of SIFT, we design and synthesize a core with SIFT logic and show that the area overhead of SIFT is only 4.5 percent and that instruction generation can be performed in one additional cycle at commit time.

Saving disk energy in video servers by combining caching and prefetching

Maintenance and upgrades to the significant storage infrastructure in a video server often create a heterogenous disk array. We show how to manage the energy consumption of such an array by combining caching and prefetching techniques. We first examine how seek operations affect disk energy consumption, and then analyze the relationship between the amount of prefetched data and the number of seeks, and the effect of the size of the prefetching buffer on energy consumption. Based on this, we propose a new data prefetching scheme in which the amount of data prefetched for each video stream is dynamically adjusted to allow for the bit-rates of streams and the power characteristics of different disks. We next examine the impact of caching on disk power consumption and propose a new caching scheme that prioritizes each stream based on the ratio of the amount of energy that can be saved to its cache requirement, so as to make effective use of limited caching space. We address the trade-off between caching and prefetching and propose an algorithm that dynamically divides the entire buffer space into prefetching and caching regions, with the aim of minimizing overall disk energy consumption. Experimental results show that our scheme can reduce disk energy consumption between 26% and 31%, compared to a server without prefetching and caching.

An adaptive multimedia streaming dissemination system for vehicular networks

An adaptive seamless streaming dissemination system for vehicular networks is presented in this work. An adaptive streaming system is established at each local server to prefetch and buffer stream data. The adaptive streaming system computes the parts of prefetched stream data for each user and stores them temporarily at the local server, based on current situation of the users and the environments where they are located. Thus, users can download the prefetched stream data from the local servers instead of from the Internet directly, meaning that the video playing problem caused by network congestion can be avoided. Several techniques such as stream data prefetching, stream data forwarding, and adaptive dynamic decoding were utilized for enhancing the adaptability of different users and environments and achieving the best transmission efficiency. Fuzzy logic inference systems are utilized to determine if a roadside base station or a vehicle can be chosen to transfer stream data for users. Considering the uneven deployment of BSs and vehicles, a bandwidth reservation mechanism for premium users was proposed to ensure the QoS of the stream data premium users received. A series of simulations were conducted, with the experimental results verifying the effectiveness and feasibility of the proposed work.

Orchestrated scheduling and prefetching for GPGPUs

In this paper, we present techniques that coordinate the thread scheduling and prefetching decisions in a General Purpose Graphics Processing Unit (GPGPU) architecture to better tolerate long memory latencies. We demonstrate that existing warp scheduling policies in GPGPU architectures are unable to effectively incorporate data prefetching. The main reason is that they schedule consecutive warps, which are likely to access nearby cache blocks and thus prefetch accurately for one another, back-to-back in consecutive cycles. This either 1) causes prefetches to be generated by a warp too close to the time their corresponding addresses are actually demanded by another warp, or 2) requires sophisticated prefetcher designs to correctly predict the addresses required by a future "far-ahead" warp while executing the current warp. We propose a new prefetch-aware warp scheduling policy that overcomes these problems. The key idea is to separate in time the scheduling of consecutive warps such that they are not executed back-to-back. We show that this policy not only enables a simple prefetcher to be effective in tolerating memory latencies but also improves memory bank parallelism, even when prefetching is not employed. Experimental evaluations across a diverse set of applications on a 30-core simulated GPGPU platform demonstrate that the prefetch-aware warp scheduler provides 25% and 7% average performance improvement over baselines that employ prefetching in conjunction with, respectively, the commonly-employed round-robin scheduler or the recently-proposed two-level warp scheduler. Moreover, when prefetching is not employed, the prefetch-aware warp scheduler provides higher performance than both of these baseline schedulers as it better exploits memory bank parallelism.

High-throughput Analysis of Large Microscopy Image Datasets on CPU-GPU Cluster Platforms.

Analysis of large pathology image datasets offers significant opportunities for the investigation of disease morphology, but the resource requirements of analysis pipelines limit the scale of such studies. Motivated by a brain cancer study, we propose and evaluate a parallel image analysis application pipeline for high throughput computation of large datasets of high resolution pathology tissue images on distributed CPU-GPU platforms. To achieve efficient execution on these hybrid systems, we have built runtime support that allows us to express the cancer image analysis application as a hierarchical data processing pipeline. The application is implemented as a coarse-grain pipeline of stages, where each stage may be further partitioned into another pipeline of fine-grain operations. The fine-grain operations are efficiently managed and scheduled for computation on CPUs and GPUs using performance aware scheduling techniques along with several optimizations, including architecture aware process placement, data locality conscious task assignment, data prefetching, and asynchronous data copy. These optimizations are employed to maximize the utilization of the aggregate computing power of CPUs and GPUs and minimize data copy overheads. Our experimental evaluation shows that the cooperative use of CPUs and GPUs achieves significant improvements on top of GPU-only versions (up to 1.6×) and that the execution of the application as a set of fine-grain operations provides more opportunities for runtime optimizations and attains better performance than coarser-grain, monolithic implementations used in other works. An implementation of the cancer image analysis pipeline using the runtime support was able to process an image dataset consisting of 36,848 4Kx4K-pixel image tiles (about 1.8TB uncompressed) in less than 4 minutes (150 tiles/second) on 100 nodes of a state-of-the-art hybrid cluster system.

Enabling Efficient WiFi-Based Vehicular Content Distribution

For better road safety and driving experience, content distribution for vehicle users through roadside Access Points (APs) becomes an important and promising complement to 3G and other cellular networks. In this paper, we introduce Cooperative Content Distribution System for Vehicles (CCDSV) which operates upon a network of infrastructure APs to collaboratively distribute contents to moving vehicles. CCDSV solves several important issues in a practical system, like the robustness to mobility prediction errors, limited resources of APs and the shared content distribution. Our system organizes the cooperative APs into a novel structure, namely, the contact map which is based on the vehicular contact patterns observed by APs. To fully utilize the wireless bandwidth provided by APs, we propose a representative-based prefetching mechanism, in which a set of representative APs are carefully selected and then share their prefetched data with others. The selection process explicitly takes into account the AP's storage capacity, storage status, inter-APs bandwidth and traffic loads on the backhaul links. We apply network coding in CCDSV to augment the distribution of shared contents. The selection of shared contents to be prefetched on an AP is based on the storage status of neighboring APs in the contact map in order to increase the information utility of each prefetched data piece. Through extensive simulations, CCDSV proves its effectiveness in vehicular content distribution under various scenarios.

Voluntary Disconnected Operations for Energy Efficient Mobile Devices in Pervasive Computing Environments

It is important to support disconnected operations in mobile computing, because wireless communication requires substantial power consumption by mobile devices. Suitable usage of voluntary disconnected operations with pre-fetching of data in mobile environments can effectively save energy and money for mobile devices in wireless pervasive computing. In this paper, we analyze energy expenditure, including voluntary disconnected operations, to evaluate the energy efficiency of mobile computing. We estimate the energy expenditure using various parameters. The results of our analysis will assist efficient employment of disconnected operations and performance prediction.

Constructing and Rendering of Multiresolution Representation for Massive Meshes with GPU and Mesh Layout

Multiresolution technique is one of the most efficient approaches to improve the rendering performance, but its design and implementation for massive meshes are still very difficult. This paper researches and realizes constructing and rendering of multiresolution representation for massive meshes base on surface partition, which could provide vertex-grained local refinement and generate the optimal rendering quality. Our approach adopts dual hierarchy to represent the mesh. One is cluster hierarchy of progressive meshes for coarse-grained selective refinement. The other is vertex hierarchy built with progressive mesh in the cluster node to provide fine-grained local refinement. In order to promote the speed of local refinement, we introduce some data structures and dependency rules to realize parallel view-dependent refinement for vertex hierarchy by using GPU, which greatly reduces the load of CPU and enables it to prefetch data to hide I/O latency effectively. In addition, we propose a new mesh layout algorithm which reorders triangles contained by cluster node to reduce the average cache miss ratio and further improve the rendering speed.

Intersection between Bi-cubic Bezier Curved Surface and Plane

The paper presents a solution to calculate intersection between a plane and bi-cubic Bezier curved surface. The paper first constructs bounding box based on the control grid by the characteristics of the Bezier surface, and then makes use of the plane half-space properties to convert the problem that calculates the intersection line between the plane and the parameter curved surface into calculating a series of intersection points by using the method that apply the bi-linear interpolation algorithm to the curved surface in representation of parameter area. The intersection line between the plane and the surface can be calculated by connecting the intersection points. This method can solve the surface intersection line well whether the line is discontinuous or form a closed cycle. The algorithm is relatively simple, and has good adaptability for calculating the intersection line between the plane and the curved surface. urround��dr����I�o-page-border-surround-footer:no;} @page Section1 {size:612.0pt 792.0pt; margin:72.0pt 90.0pt 72.0pt 90.0pt; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} --> Multiresolution technique is one of the most efficient approaches to improve the rendering performance, but its design and implementation for massive meshes are still very difficult. This paper researches and realizes constructing and rendering of multiresolution representation for massive meshes base on surface partition, which could provide vertex-grained local refinement and generate the optimal rendering quality. Our approach adopts dual hierarchy to represent the mesh. One is cluster hierarchy of progressive meshes for coarse-grained selective refinement. The other is vertex hierarchy built with progressive mesh in the cluster node to provide fine-grained local refinement. In order to promote the speed of local refinement, we introduce some data structures and dependency rules to realize parallel view-dependent refinement for vertex hierarchy by using GPU, which greatly reduces the load of CPU and enables it to prefetch data to hide I/O latency effectively. In addition, we propose a new mesh layout algorithm which reorders triangles contained by cluster node to reduce the average cache miss ratio and further improve the rendering speed.

SCOUT

Today's scientists are quickly moving from in vitro to in silico experimentation: they no longer analyze natural phenomena in a petri dish, but instead they build models and simulate them. Managing and analyzing the massive amounts of data involved in simulations is a major task. Yet, they lack the tools to efficiently work with data of this size. One problem many scientists share is the analysis of the massive spatial models they build. For several types of analysis they need to interactively follow the structures in the spatial model, e.g., the arterial tree, neuron fibers, etc., and issue range queries along the way. Each query takes long to execute, and the total time for executing a sequence of queries significantly delays data analysis. Prefetching the spatial data reduces the response time considerably, but known approaches do not prefetch with high accuracy. We develop SCOUT, a structure-aware method for prefetching data along interactive spatial query sequences. SCOUT uses an approximate graph model of the structures involved in past queries and attempts to identify what particular structure the user follows. Our experiments with neuro-science data show that SCOUT prefetches with an accuracy from 71% to 92%, which translates to a speedup of 4x-15x. SCOUT also improves the prefetching accuracy on datasets from other scientific domains, such as medicine and biology.

Algorithm-level Feedback-controlled Adaptive data prefetcher: Accelerating data access for high-performance processors

The rapid advance of processor architectures such as the emerged multicore architectures and the substantially increased computing capability on chip have put more pressure on the sluggish memory systems than ever. In the meantime, many applications become more and more data intensive. Data-access delay, not the processor speed, becomes the leading performance bottleneck of high-performance computing. Data prefetching is an effective solution to accelerating applications' data access and bridging the growing gap between computing speed and data-access speed. Existing works of prefetching, however, are very conservative in general, due to the computing power consumption concern of the past. They suffer low effectiveness especially when applications' access pattern changes. In this study, we propose an Algorithm-level Feedback-controlled Adaptive (AFA) data prefetcher to address these issues. The AFA prefetcher is based on the Data-Access History Cache, a hardware structure that is specifically designed for data access acceleration. It provides an algorithm-level adaptation and is capable of dynamically adapting to appropriate prefetching algorithms at runtime. We have conducted extensive simulation testing with the SimpleScalar simulator to validate the design and to analyze the performance gain. The simulation results show that the AFA prefetcher is effective and achieves considerable IPC (Instructions Per Cycle) improvement for 21 representative SPEC-CPU benchmarks.

A hybrid storage technology for low power consumption and high I/O performance in an IPTV set-top box

A new method of prefetching data blocks from the NVCache to the page cache in main memory and cascading prefetching n-blocks from a hard disk to the NVCache together was proposed to reduce the spin-up frequency of a hybrid hard disk drive and thus enhance I/O performance. The proposed method consists of three steps: 1) Analyzing the pattern of read requests in block units; 2) Determining the number of blocks prefetched to the NVCache; 3) Replacing blocks in the NVCache according to the block replacement policy. The proposed method can reduce the latency time of a hybrid hard disk and optimize the power consumption of an IPTV set-top box. Experimental results show that the proposed method provides better average response time compared to an existing adaptive multistream prefetching (AMP) method by 25.17%. It also reduces by 20.83% the average power consumption over that of the existing external caching in energy saving storage system (EXCES) method.

ASEP: An Adaptive Sequential Prefetching Scheme for Second-level Storage System

In model storage systems, the multilevel buffer caches hierarchy is widely used to improve the I/O performance of disks. In the hierarchy, the referenced pages in second-level buffer cache have larger reuse distance that is the number of accesses between two references to the same block in a reference sequence. These reuse distances have close value with their lifetime- the time they are conserved in buffer cache. Therefore, this tiny difference can be more easily eliminated by the prefetched (not yet accessed) data that reduces the lifetime of referenced pages. This leads more pages than those replaced by prefetching to lose their re-access opportunity. This anomaly influence can significantly reduce the overall hit ratio of buffer cache and, unfortunately, it is ignored by traditional sequential prefetching algorithms. To address this problem, we propose an Adaptive SEquential Prefetching (named ASEP) that uncovers this anomaly influence and adaptively adjusts the prefetching depth by considering the access characteristics in second-level buffer cache. We extensively evaluate ASEP by conducting trace driven experiments with a prototype implements in Linux (software RAID-MD). The experiments’ results, under varied workloads from transaction processing applications to Web searching applications, show that ASEP outperforms the default sequential prefetching scheme in Linux kernel and other heuristic schemes, with the response time improvement by up to 49.7% and the cache hit ratio improvement ranging from 0.2~ 8.5%.

ABS

Hardware data prefetch is a very well known technique for hiding memory latencies. However, in a multicore system fitted with a shared Last-Level Cache (LLC), prefetch induced by a core consumes common resources such as shared cache space and main memory bandwidth. This may degrade the performance of other cores and even the overall system performance unless the prefetch aggressiveness of each core is controlled from a system standpoint. On the other hand, LLCs in commercial chip multiprocessors are more and more frequently organized in independent banks. In this contribution, we target for the first time prefetch in a banked LLC organization and propose ABS, a low-cost controller with a hill-climbing approach that runs stand-alone at each LLC bank without requiring inter-bank communication. Using multiprogrammed SPEC2K6 workloads, our analysis shows that the mechanism improves both user-oriented metrics (Harmonic Mean of Speedups by 27% and Fairness by 11%) and system-oriented metrics (Weighted Speedup increases 22% and Memory Bandwidth Consumption decreases 14%) over an eight-core baseline system that uses aggressive sequential prefetch with a fixed degree. Similar conclusions can be drawn by varying the number of cores or the LLC size, when running parallel applications, or when other prefetch engines are controlled.