Data Plane Development Kit Research Articles

A Generic High-Performance Architecture for VPN Gateways

Virtual private network (VPN) gateways are widely applied to provide secure end-to-end remote access and to relay reliable interconnected communication in cloud computing. As network convergence nodes, the performance of VPN gateways is limited by traditional methods of packet receiving and sending, the kernel protocol stack and the virtual network interface card. This paper proposes a generic high-performance architecture (GHPA) for VPN gateways in consideration of its generality and performance. In terms of generality, we redesign a generic VPN core framework by modeling a generic VPN communication model, formulating generic VPN core technologies and presenting corresponding core algorithms. In terms of performance, we propose a three-layer GHPA for VPN gateways by designing a VPN packet processing layer based on a data plane development kit (DPDK), implementing a user space basic protocol stack and applying our proposed generic VPN core framework. On the basis of the research work above, we implement a high-performance VPN (HP-VPN) and a traditional VPN (T-VPN) that complies with GHPA and traditional methods, respectively. Experimental results prove that the performance of HP-VPN based on GHPA is superior to T-VPN and other common VPNs in RTT, system throughput, packet forwarding rate and jitter. In addition, GHPA is extensible and applicable for other VPN gateways to improve their performance.

Hardware nanosecond‐precision timestamping for line‐rate packet capture

AbstractCybersecurity events occur frequently. When it comes to investigating security threats, it is essential to offer a 100 percent accurate and packet‐level network history, which depends on packet capture with high precision packet timestamping. Many packet capture applications are developed based on data plane development kit (DPDK)—a set of libraries and drivers for fast packet processing. However, DPDK cannot give an accurate timestamp for every packet, and it is unable to truly reflect the order in which packets arrive at the network interface card. In addition, DPDK‐based applications cannot achieve zero packet loss when the packet is small such as 64 B for beyond 10 Gigabit Ethernet. Therefore, the authors proposed a new method based on Field‐Programmable Gate Array (FPGA) to solve this problem. The authors also develop a DPDK driver for FPGA devices to make the design compatible with all DPDK‐based applications. The proposed method performs timestamping at line‐rate for 10 Gigabit Ethernet traffic at 4 ns precision and 1 ns precision for 25 Gigabit, which greatly improves the accuracy of security incident retrospective analysis. Furthermore, the design can capture full‐size packets for any protocol with zero packet loss and can be applied to 40/100 Gigabit systems as well.

MiddleNet: A Unified, High-Performance NFV and Middlebox Framework With eBPF and DPDK

Traditional network resident functions (e.g., firewalls, network address translation) and middleboxes (caches, load balancers) have moved from purpose-built appliances to softwarebased components. However, L2/L3 network functions (NFs) are being implemented on Network Function Virtualization (NFV) platforms that extensively exploit kernel-bypass technology. They often use DPDK for zero-copy delivery and high performance. On the other hand, L4/L7 middleboxes, which have a greater emphasis on functionality, take advantage of a full-fledged kernelbased system. L2/L3 NFs and L4/L7 middleboxes continue to be handled by distinct platforms on different nodes. This paper proposes MiddleNet that develops a unified network resident function framework that supports L2/L3 NFs and L4/L7 middleboxes. MiddleNet supports function chains that are essential in both NFV and middlebox environments. MiddleNet uses the Data Plane Development Kit (DPDK) library for zero-copy packet delivery without interrupt-based processing, to enable the ’bumpin-the-wire’ L2/L3 processing performance required of NFV. To support L4/L7 middlebox functionality, MiddleNet utilizes a consolidated, kernel-based protocol stack for processing, avoiding a dedicated protocol stack for each function. MiddleNet fully exploits the event-driven capabilities of the extended Berkeley Packet Filter (eBPF) and seamlessly integrates it with shared memory for high-performance communication in L4/L7 middlebox function chains. The overheads for MiddleNet in L4/L7 are strictly load-proportional, without needing the dedicated CPU cores of DPDK-based approaches. MiddleNet supports flow-dependent packet processing by leveraging Single Root I/O Virtualization (SR-IOV) to dynamically select the packet processing needed (Layers 2 -7). Our experimental results show that MiddleNet achieves high performance in such a unified environment.

An Optimization Method of Large-Scale Video Stream Concurrent Transmission for Edge Computing

Concurrent access to large-scale video data streams in edge computing is an important application scenario that currently faces a high cost of network access equipment and high data packet loss rate. To solve this problem, a low-cost link aggregation video stream data concurrent transmission method is proposed. Data Plane Development Kit (DPDK) technology supports the concurrent receiving and forwarding function of multiple Network Interface Cards (NICs). The Q-learning data stream scheduling model is proposed to solve the load scheduling of multiple queues of multiple NICs. The Central Processing Unit (CPU) transmission processing unit was dynamically selected by data stream classification, as well as a reward function, to achieve the dynamic load balancing of data stream transmission. The experiments conducted demonstrate that this method expands the bandwidth by 3.6 times over the benchmark scheme for a single network port, and reduces the average CPU load ratio by 18%. Compared to the UDP and DPDK schemes, it lowers the average system latency by 21%, reduces the data transmission packet loss rate by 0.48%, and improves the overall system transmission throughput. This transmission optimization scheme can be applied in data centers and edge computing clusters to improve the communication performance of big data processing.

RETRACTED ARTICLE: Internet financial forecasting and digital economy development by using machine learning algorithm in the new consumption environment

Data plane development kit (DPDK) provides an effective solution for the rapid processing of general multi-core processor platforms. Research based on DPDK on a general-purpose multi-core processor platform can use CPU cache to improve packet forwarding and processor core performance, as well as network function virtualization performance. In the parallel development of finance and network, people find that complex financial problems can be well-solved through big data network. The rapidly changing financial market is affected by economic and political factors, and the generation of financial data is also highly uncertain. However, financial forecast analysis and forecast modeling are of great significance. As a whole, this trend could help inform policy; from a meso-level, it can be insightful. The changes in financial data are conducive to the planning of business strategies for enterprises and gaining market competitive advantages; from a micro-level, individual investors will pay attention to historical data changes and the development of industries or companies before making investment decisions in order to obtain benefits. Internet technology can strengthen the accuracy of financial forecasting, so as to effectively avoid risks, but also can promote the development of digital economy, reduce labor costs, improve the breadth and depth of financial services in digital economy.

Real-time data processing for ultrafast X-ray computed tomography using modular CUDA based pipelines

In this article, a new version of the Real-time Image Stream Algorithms (RISA) data processing suite is introduced. It now features online detector data acquisition, high-throughput data dumping and enhanced real-time data processing capabilities. The achieved low-latency real-time data processing extends the application of ultrafast electron beam X-ray computed tomography (UFXCT) scanners to real-time scanner control and process control. We implemented high performance data packet reception based on data plane development kit (DPDK) and high-throughput data storing using both hierarchical data format version 5 (HDF5) as well as the adaptable input/output system version 2 (ADIOS2). Furthermore, we extended RISA's underlying pipelining framework to support the fork-join paradigm. This allows for more complex workflows as it is necessary, e.g. for online data processing. Also, the pipeline configuration is moved from compile-time to runtime, i.e. processing stages and their interconnections can now be configured using a configuration file. In several benchmarks, RISA is profiled regarding data acquisition performance, data storage throughput and overall processing latency. We found that using direct IO mode significantly improves data writing performance on the local data storage. We could further prove that RISA is now capable of concurrently receiving, processing and storing data from up to 768 detector channels (3072 MB/s) at 8000 fps on a single-GPU computer in real-time. Program summaryProgram Title: GLADOS/RISACPC Library link to program files:https://doi.org/10.17632/65sx747rvm.2Developer's repository link:https://codebase.helmholtz.cloud/risaLicensing provisions: Apache-2.0Programming language: C++Journal reference of previous version: Comput. Phys. Commun. 219 (2017) 353-360 [1]Does the new version supersede the previous version?: Yes.Reasons for the new version: Extended capabilities for real-time operation with latest UFXCT hardware.Summary of revisions: (i) Add forking and joining of processing pipeline branches(ii) Add runtime (re-)configuration of pipeline stages and connections(iii) Add UDP receiver stage to acquire detector data in real-time(iv) Add high-throughput data dumpingNature of problem: Ultrafast electron beam X-ray computed tomography scanners stream multiple Gigabytes of raw data per second via Ethernet to a control computer. Receiving the data with low latency, real-time image-based control would become possible. For this, data need to be captured from the network, stored on disk, reconstructed and post-processed concurrently. The current total data rate of up to 3072 MB/s requires high-throughput solutions for each of these tasks.Solution method: Using a pipeline scheme, RISA processes incoming raw data in distinct stages (sources, processors, sinks). These are implemented in GPU kernels and are executed concurrently to exploit data parallelism as well as task parallelism. To capture detector data, we implemented a UDP packet capturing stage based on DPDK [2] which acts as a source stage. By allowing the pipeline to fork up into multiple branches, we concurrently acquire, store and process the data. For storing these data, we use the HDF5 format [3]. We achieve the required data rates by writing in direct IO mode onto an SSD array in RAID 0 configuration.Additional comments including restrictions and unusual features: RISA provides a set of general-purpose processing stages which are suitable for generic image stream processing.

MVPN: A Defense Architecture against VPN Traffic Hijacking Based on MTD

With the increasing awareness of privacy protection, Virtual Private Networks (VPNs) are widely used to build a more secure communication tunnel. However, a traffic hijacking attack called blind in/on-path has seriously threatened the security of VPNs. Inspired by Moving Target Defense (MTD), Moving VPN architecture (MVPN) is designed to defend against such attacks. MVPN includes multiple nodes to encrypt and decrypt traffic to enhance reliability. Thus, the consistency judgment algorithm is proposed to make MVPN obtain the ability to perceive attacks. Moreover, according to the judgment result and the state update strategy, the MVPN state is dynamically changed so as to achieve the purpose of active defense. In addition, this paper also designs the multichannel packet classification mechanism and availability assurance strategy, which not only ensures the security and availability of the system but also reduces the performance loss caused by the defense strategy. The simulation verifies that MVPN architecture can reduce the success rate of blind in/on-path attacks by five orders of magnitude. In addition, we implemented and deployed MVPN based on the fast-forwarding framework of the Data Plane Development Kit (DPDK). Experiments in the real environment also show that the MVPN system can effectively prevent attackers from carrying out blind in/on-path attacks.

Integrated SDN-NFV 5G Network Performance and Management-Complexity Evaluation

Digitalization is one of the factors that affects the acceleration of the application of telecommunications technologies such as 5G. The 5G technology that has been developed today does not yet meet different performance and manageability standards, particularly for data center networks as a supportive technology. Software-defined networking (SDN) and network function virtualization (NFV) are two complementary technologies that are currently used by almost all data centers in the telecommunications industry to rectify performance and manageability issues. In this study, we deliver an integrated SDN-NFV architecture to simplify network management activities in telecommunication companies. To improve network performance at the computing level, we performed a modification of a networking system at the computing level, underlying NFV devices by replacing the default virtual switch with a data plane development kit (DPDK) and single root I/O virtualization (SR-IOV). This study evaluated the proposed architecture design in terms of network performance and manageability. Based on 30 days of observation in prime time, the proposed solution increased throughput up to 200 Mbps for the server leaf and 1.6 Gbps for the border leaf compared to the legacy architecture. Meanwhile, the latency decreased to 12 ms for the server leaf and 17 ms for the border leaf. For manageability, we tested three different scenarios and achieved savings of 13 min for Scenario 1, 22 min for Scenario 2 and 9 min for Scenario 3.

Performance analysis of DPDK-based applications through tracing

The Data Plane Development Kit (DPDK) is an efficient framework developed based on the kernel bypass approach to accelerate packet processing in userspace. This framework includes many libraries and Poll Mode Drivers (PMDs) that are optimized for maximum network performance. Several studies have demonstrated that porting existing data plane applications to DPDK can considerably increase their performance. Unfortunately, kernel bypassing makes traditional network monitoring and debugging tools obsolete. Therefore, considering the complexity of networking software, detecting unexpected behaviors, and diagnosing its root causes became a tedious task. The literature reports a few tools intended for debugging DPDK application bugs, but they are mostly ineffective against performance bugs.In this paper, we propose a tracing-based performance analysis framework that is dedicated to DPDK applications. The framework provides many analyses enabling the practitioner to gain insights into the application internals and diagnose performance bugs. We use an efficient approach to collect tracing data from DPDK libraries and drivers, with a very low overhead (<0.2%). Our framework correlates the data collected to build a data model that illustrates the states of the monitored application' components. We leverage this data model to calculate adapted performance metrics and display them in time-synchronized graphical views. The numerous use cases that we present demonstrate the ability of our tool to identify and diagnose efficiently various performance bugs.

Takeaways from an experimental evaluation of eXpress Data Path (XDP) and Data Plane Development Kit (DPDK) under a Cloud Computing environment

The popularization of the Linux kernel at data center servers became a significant factor to consider when developing or deploying network applications. New “packet processing frameworks” emerged to ensure fast packet processing inside these servers that rely on the Linux kernel, XDP and DPDK being the two main ones. Alongside this, Cloud Computing environments dominated the data center scenario, bringing virtualization to the center of these servers. This research compares DPDK and XDP packet processors when subject to a cloud computing environment with I/O, CPU, and network load. We first describe an architecture that implements frameworks and emulates a cloud environment. We measure throughput and packet loss while varying the number of competing VMs, CPU usage by the frameworks, and packet size and present our results in the form of takeaways. Furthermore, we conclude that the virtual environment can impact the performance of both frameworks depending on the received packet size and the type of workload the cloud environment performs. A significant case to highlight is when the cloud environment performs network load, and the servers receive small-sized packets, creating both throughput degradation and increasing packet loss. We conclude our experiments by conducting statistical non-parametric hypothesis tests to enhance our conclusions and have a closer look at the results.

Traditional vs. Modern Data Paths: A Comprehensive Survey

Recently, many new network paths have been introduced while old paths are still in use. The trade-offs remain vague and should be further addressed. Since last decade, the Internet is playing a major role in people’s lives, and the demand on the Internet in all fields has increased rapidly. In order to get a fast and secure connection to the Internet, the networks providing the service should get faster and more reliable. Many network data paths have been proposed in order to achieve the previous objectives since the 1970s. It started with the Transmission Control Protocol (TCP) and the User Datagram Protocol (UDP) and later followed by several more modern paths including Quick UDP Internet Connections (QUIC), remote direct memory access (RDMA), and the Data Plane Development Kit (DPDK). This raised the question on which data path should be adopted and based on which features. In this work, we try to answer this question using different perspectives such as the protocol techniques, latency and congestion control, head of line blocking, the achieved throughput, middleboxes consideration, loss recovery mechanisms, developer productivity, host resources utilization and targeted application.

Design and Implementation of Enhanced Programmable Data Plane Supporting ICN Mobility

Information-centric networking (ICN) separates the identifier and locator of network entities, providing a natural advantage in supporting mobility. To gain the advantage of ICN to support mobility, an urgent challenge is the problem of practical implementation with performance optimization. Software-defined networking (SDN) can be regarded as infrastructure to implement ICN mobility. However, it is difficult for the centralized SDN controller to quickly process mobile signaling. Therefore, this paper proposes enhanced programmable data plane supporting ICN mobility. By offloading mobility-related control plane functions from the controller to the data plane, the data plane can locally process mobile signaling without interacting with the controller. We propose an offloading mechanism for control plane functions, based on a rule table, where the controller authorizes the data plane to process the mobile signaling by loading the programmable rule table to data plane’s control element, and the control element intercepts the mobile signaling, matches the predefined rule table, and executes a series of application logic actions. In addition, we propose an improved SmartSplit algorithm to manage the rule table and speed up packets matching the rule table. Based on Intel’s Data Plane Development Kit (DPDK), we implement the enhanced programmable data plane. Our experimental results prove that the proposed enhanced programmable data plane has a stronger ability to process mobile signaling and reduce latency.

Virtualizing GPU direct packet I/O on commodity Ethernet to accelerate GPU-NFV

Network functions (NFs) play an important role in the rapid and dynamic deployment of various services. Network function virtualization (NFV) on commodity servers is becoming popular; and is associated with benefits in terms of cost, elasticity, and liveness, instead of dedicated hardware middleboxes. In this recent trend, graphics processing units (GPUs) have been shown to be highly suitable for NF acceleration, owing to their high parallelism and memory bandwidth. This paper proposes a new GPU-NFV architecture called Janus to accelerate NFs in virtualized environments. Janus is an extension of a previous study conducted by the present authors and involves GPU direct packet input/output (I/O) on commodity Ethernet, to a virtualization environment. Janus uses single-root I/O virtualization (SR-IOV) to enable high-performance NIC sharing between the host and guest virtual machine running GPU direct packet I/O. Internally, the received packets for GPU-NFV are transferred to the GPU memory directly through a combination of SR-IOV and peer-to-peer DMA. The evaluation results show that Janus’ GPU-NFV performance is up to 2.3x higher than that of the state-of-the-art data-plane development kit (DPDK).

Design and implementation of a software tester for benchmarking stateful NATxy gateways: Theory and practice of extending siitperf for stateful tests

Our siitperf is the world’s first RFC 8219 compliant free software SIIT (Stateless IP/ICMP Translation, also called stateless NAT64) benchmarking tool. It was written in C++ using DPDK (Intel Data Plane Development Kit). Our current effort aims to design and implement a test program for stateful NATxy gateways, including both stateful NAT64 and stateful NAT44 (also called NAPT: Network Address and Port Translation). Due to the object-oriented design of siitperf, it is feasible to extend it for stateful tests, while keeping its original design and features. In this paper, we introduce the problem of benchmarking stateful NATxy gateways and propose various solutions. We disclose the design and the most important implementation decisions of the stateful extension of siitperf. We prove the viability of our design and implementation by a functional NAT64 test and performing the maximum connection establishment rate, throughput, and frame loss rate measurements of the Jool stateful NAT64 implementation. We also carry out an initial performance estimation of the stateful extension of siitperf. Our tester is distributed as free software under the GPLv3 license for the benefit of the research, benchmarking and networking communities.

Design and Implementation of Programmable Data Plane Supporting Multiple Data Types

Software-defined networking (SDN) separates the control plane and the data plane, which provides network applications with global network topology and the flexibility to customize packet forwarding rules. SDN has a wide range of innovative applications in 5G, Internet of Things, and information center networks. However, the match-action programming model represented by OpenFlow/Protocol Oblivious Forwarding (POF) in SDN can only process limited types of data such as packets and metadata, making it hard to fulfill future network applications. In this paper, data type and data location are added in the matching fields and actions to make the match-action table (MAT) compatible with multiple types of data, hence improving the data plane’s programmability. Data type helps the MAT to perceive multiple types of data, allowing them to be processed by a single MAT. Data location allows MAT to be decoupled from data meaning, quickly locating specific data in the switch. Based on Intel’s Data Plane Development Kit (DPDK), we design and implement a pipeline that is compatible with multiple types of data processing. Protocol and data type oblivious match-action tables and atomic instructions are included in the pipeline. Experiments show that representing data with data type and data location makes the pipeline compatible with multiple types of data without sacrificing forwarding performance, fulfilling the needs of network applications to handle a variety of types of data while avoiding repeating hardware design.

Sphinx: A transport protocol for high-speed and lossy mobile networks

Modern mobile wireless networks have been demonstrated to be high-speed but lossy, while mobile applications have more strict requirements including reliability, low latency, goodput guarantee, bandwidth efficiency, and computation efficiency. Such a complicated combination of requirements and conditions in networks pushes the pressure to transport layer protocol design. We analyze and argue that few of existing network transport layer solutions are able to handle all these requirements. We design and implement Sphinx to satisfy the five requirements in high-speed and lossy networks. Sphinx has (1) a proactive coding-based method named semi-random LT codes for loss recovery, which estimates packet loss rate and adjusts the redundancy level accordingly, (2) a reactive retransmission method named Instantaneous Compensation Mechanism (ICM), which retransmits precisely and timely once decoding failure occurs, and (3) a parallel coding architecture, which speeds up coding process by leveraging multi-core, shared memory and kernel-bypass Data Plane Development Kit (DPDK). Prototype and evaluation show that Sphinx outperforms TCP schemes and other coding solutions significantly in microbenchmarks across all five requirements, and improves the performance of the video streaming application.

An Efficient IDS Framework for DDoS Attacks in SDN Environment

The rapid usage of the Internet for the last few decades has lead to the deployment of high-speed networks in commercial and educational institutions. As network traffic is increasing, security challenges are also increasing in the high-speed network. Although the Intrusion Detection System (IDS) has a significant role in spotting potential attacks, the heavy traffic flow causes severe technical challenges relating to monitoring and detecting the network activities. Moreover, the devastating nature of the Distributed Denial-of-Service (DDoS) attack draws out as a significant cyber-attack regardless of the emergence of Software Defined Network (SDN) architecture. This paper proposes a novel framework to address the performance issues of IDS and the design issues of SDN about DDoS attacks by incorporating intelligence in the data layer using Data Plane Development Kit (DPDK) in the SDN architecture. This novel framework is named as DPDK based DDoS Detection (D3) framework, since DPDK provides fast packet processing and monitoring in the data plane. Moreover, the statistical anomaly detection algorithm implemented in the data plane as Virtual Network Function (VNF) using DPDK offers fast detection of DDoS attacks. The experimental results of the D3 framework guarantee both efficiency and effect of the novel IDS framework. The publicly available CIC DoS datasets also ensure the detection effect of a single statistical anomaly detection algorithm against the DDoS attack.

An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning

In distributed deep neural network using remote GPU nodes, communication occurs iteratively between remote nodes for gradient aggregation. This communication latency limits the benefit of distributed training with faster GPUs. In this paper, we therefore propose to offload the gradient aggregation to a DPDK (Data Plane Development Kit) based network switch between a host machine and remote GPUs. In this approach, the aggregation process is completed in the network using extra computation resources in the network switch and efficiently overlapped without increasing workload on remote nodes. The proposed DPDK-based switch supports reliable communication protocols for exchanging gradients data and can handle a part of MPI over TCP-based communication. We evaluate the proposed switch when GPUs and the host communicate with a standard IP communication over 40GbE, a PCI Express (PCIe) over 40Gbit Ethernet (40GbE) product and MPI communication over 10GbE, respectively. The evaluation results using a standard IP communication show that the aggregation is accelerated by 2.2-2.5x compared to the aggregation executed by a host machine. The results using the PCIe over 40GbE product show that the proposed switch outperforms the aggregation done by the host machine by 1.16x. The evaluations using MPI communication using Jetson Xaviers cluster show that the proposed switch provides up to 5.5-5.8x faster reduction operations than the conventional method.

High‐performance user plane function (UPF) for the next generation core networks

Comparing with previous mobile communications, the fifth generation (5G) mobile communication provides three different types of services including enhanced mobile broadband, massive machine type communications, and ultra-reliable and low latency communications. To fulfil various requirements of these services, 5G defines new technologies and architectures such as the next-generation core network (NGC) and the new radio of the access network (5G-AN). The user plane function (UPF), which is an essential component in 5G NGC, connects 5G-AN and packet data networks (e.g. internet). Typically, the UPF provides the tunnelling, internet protocol/port translation, and forwarding functions. To provide flexibility and scalability deployment for 5G NGC, this study virtualises the UPF by using the Docker container. However, the virtualisation architecture degrades the performance of the UPF, and the performance of the UPF dominates the performance (e.g. throughput) of the 5G user-plane transmission. To provide high-performance packet processing, this study utilises Intel Data Plane Development Kit to develop the UPF, reduces the number of memory copy on header processing, and investigates the CPU core allocation methods for the UPF deployment. Based on the results of this study, the proposed UPF can provide the UPF functions and process the packets up to 40 Gbps on a x86-based platform.

Accelerating Virtual Network Functions With Fast-Slow Path Architecture Using eXpress Data Path

By decoupling network functions from dedicated, proprietary hardware network devices, Network Function Virtualization (NFV) allows building Virtual Network Functions (VNFs) that can run on standard, commodity servers to reduce cost and gain flexibility in network deployment, operation, and management. However, building VNFs with high-throughput and low-latency is a big challenge. In this paper, we propose eVNF - a hybrid fast-slow path architecture to build and accelerate VNFs with eXpress Data Path (XDP), which is a Linux kernel framework that enables high performance and programmable network processing. The programmability of XDP is limited to ensure kernel safety, thus causing difficulties when using XDP to accelerate VNFs. eVNF solves this problem by taking a hybrid approach: leave the simple but critical tasks inside the kernel with XDP, and let complex tasks be processed outside XDP, e.g., in user-space. With the hybrid architecture, eVNF allows building fast and flexible VNFs. We applied eVNF to build four prototype VNFs: Flow Monitoring (eFM), Firewall (eFW), Deep Packet Inspection (eDPI), and Load Balancer (eLB). These VNFs are evaluated individually and in service function chains (SFCs) using OpenStack. Our experiments showed that eVNF can significantly improve service throughput as well as reduce latency and CPU usage. eVNF-based VNFs also can scale out with the number of CPU cores and can combine with Open vSwitch - Data Plane Development Kit (OvS-DPDK) for better performance.