Input Data Rate Research Articles

A 20-Gb/s 1 : 2 Demultiplexer With Capacitive-Splitting Current-Mode-Logic Latches

This paper presents a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-mum CMOS process. By employing a capacitive-splitting architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX. Provided a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sup> - 1 pseudorandom bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage.

All-Optical Clock Recovery Using Erbium-Doped Fiber Laser Incorporating an Electroabsorption Modulator and a Linear Optical Amplifier

We demonstrated a 10-GHz all-optical clock recovery system using an erbium-doped fiber laser that incorporates an electroabsorption modulator and a linear optical amplifier. Stable pulses with peak power of 200 mW and pulsewidth of 6 ps are obtained. The output power and the pulsewidth of the recovered clock pulses are independent of the input data pattern. Stable optical clock can still be observed when the input data rate varies by more than 60% of the fundamental frequency without any optical tunable delay line inside the laser cavity. The scheme is essentially wavelength transparent for the whole C-band which recovers clock pulses from input data wavelength between 1525 and 1565 nm

Digital isolation amplifier in silicon-on-sapphire CMOS

The design and fabrication results of a monolithic four-channel digital isolation amplifier in a 0.5 µm silicon-on-sapphire technology is reported. The isolation device is manufactured in a single die, taking advantage of the isolation properties of the sapphire substrate. The individual isolation channels can operate in excess of 40 Mbit/s using digital phase-shift-keying modulation. Modulation of the input signal is used to increase immunity to errors at low input data rates. The device can tolerate ground bounces of 1 V/µs and isolate more than 800 V.

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

This paper presents a 2-D DCT/IDCT processor chip for high data rate image processing and video coding. It uses a fully pipelined row---column decomposition method based on two 1-D DCT processors and a transpose buffer based on D-type flip-flops with a double serial input/output data-flow. The proposed architecture allows the main processing elements and arithmetic units to operate in parallel at half the frequency of the data input rate. The main characteristics are: high throughput, parallel processing, reduced internal storage, and maximum efficiency in computational elements. The processor has been implemented using standard cell design methodology in 0.35 ?m CMOS technology. It measures 6.25 mm2 (the core is 3 mm2) and contains a total of 11.7 k gates. The maximum frequency is 300 MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The computing time of a block is close to 580 ns. It has been designed to meets the demands of IEEE Std. 1,180---1,990 used in different video codecs. The good performance in the computing speed and hardware cost indicate that this processor is suitable for HDTV applications.

A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

SUMMARY A clock and data recovery (CDR) circuit using a new halfrate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the

Power Aware Attitude Computation During Rapid Rotational Motion

A technique for increasing the accuracy of attitude update calculations when data sample rates are low is described. The technique is based on the use of a fixed-point coordinate rotation digital computer (CORDIC) function. In addition to improved accuracy, power consumption is reduced at lower data rates. The technique is also useful for maintaining computational accuracy during high angular rate inputs. The result of an experiment employing microelectromechanical system (MEMS) gyroscopes and comparing the CORDIC-based method with Taylor series approximations is described. In the experiment, a second-order Taylor's series approximation resulted in computed errors in the Euler angle of greater than 5/spl deg/ and 15/spl deg/ at respective sample rates of 60 and 30 samples/s, while the CORDIC-based method was accurate to within 2 arcseconds. Power consumption estimates are provided for several input data rates for CORDIC-based field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations.

A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback

A continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described. The circuit automatically detects a change in input data rate, acquires the new frequency, and reports the data rate to the user without the need for an external reference clock or any programming. At 2.5Gb/s, it achieves an acquisition time of 1 ms. In tracking mode, it uses a dual DLL/PLL to provide superior jitter performance compared to a standard second-order loop. At the OC48 data rate, it achieves a jitter transfer bandwidth of 500 kHz and a jitter tolerance bandwidth of 3 MHz. It is on a 0.35-/spl mu/m double-poly, triple-metal (DPTM) BiCMOS process, dissipates 235 mA from a 3.3-V supply, and occupies 9 mm/sup 2/. It is in a compact 5/spl times/5 mm/sup 2/ LFCSP package.

Imaging and power generation strategies for chandrayaan-1

The Chandrayaan-1 mission proposes to put a 550 kg lunarcraft into Geostationary Transfer Orbit (GTO) using the Polar Satellite Launch Vehicle (PSLV) which will subsequently be transferred into a 100 km circular lunar polar orbit for imaging purposes. In this paper, we describe certain aspects of mission strategies which will allow optimum power generation and imaging of the lunar surface.The lunar orbit considered is circular and polar and therefore nearly perpendicular to the ecliptic plane. Unlike an Earth orbiting remote sensing satellite, the orbit plane of lunar orbiter is inertially fixed as a consequence of the very small oblateness of the Moon. The Earth rotates around the Sun once a year, resulting in an apparent motion of Sun around this orbit in a year. Two extreme situations can be identified concerning the solar illumination of the lunar orbit, noon/midnight orbit, where the Sun vector is parallel to the spacecraft orbit plane and dawn/dusk orbit, where the Sun vector is perpendicular to the spacecraft orbit plane. This scenario directly affects the solar panel configuration. In case the solar panels are not canted, during the noon/midnight orbit, 100% power is generated, whereas during the dawn/dusk orbit, zero power is generated. Hence for optimum power generation, canting of the panels is essential. Detailed analysis was carried out to fix optimum canting and also determine a strategy to maintain optimum power generation throughout the year. The analysis led to the strategy of 180‡ yaw rotation at noon/midnight orbits and flipping the solar panel by 180‡ at dawn/dusk orbits. This also resulted in the negative pitch face of the lunarcraft to be an anti-sun panel, which is very useful for thermal design, and further to meet cooling requirements of the spectrometers.In principle the Moon’s surface can be imaged in 28 days, because the orbit chosen and the payload swath provide adequate overlap. However, in reality it is not possible to complete the imaging in 28 days due to various mission constraints like maximum duration of imaging allowed keeping in view the SSR sizing and payloads data input rate, time required for downlinking the payload data, data compression requirements and visibility of the lunarcraft for the Bangalore DSN. In each cycle, all the latitudes are swept. Due to the constraints mentioned, only 60‡ latitude arc coverage is possible in each orbit. As Bangalore DSN is the only station, half of the orbits in a day are not available. The longitudinal gaps because of non-visibility are covered in the next cycle by Bangalore DSN. Hence, in the firstprime imaging season, only 25% of the prime imaging zones are covered, and an additional threeprime imaging seasons are required for a full coverage of the Moon in two years. Strategy is also planned to cover X-ray payload coverage considering swath and orbit shift.

Memory centric design of an MPEG-4 video encoder

The cost-efficient implementation of video codecs requires a set of methodologies and decision taking at different levels in the design flow. We combine upfront algorithmic tuning with memory centric optimizations to transform the video application into a system consisting of functional blocks with localized data processing and a tailored memory hierarchy. This memory optimized functional description is the leverage for the cost-efficient mapping of the system on integrated multimedia platforms. It closely reflects the real implementation constraints and consequently allows for steering the architecture selection in a correct way. The proposed approach is demonstrated on a MPEG-4 video encoder and leads to its implementation as a pipelined system. Hardware development of the motion estimation validates that the high-level memory centric concepts are applicable and realizable at the lowest level. The motion estimation kernel supports up to 30 CIF f/s with minimized processing element requirements and data input rates.

Parallel-pipeline 8/spl times/8 forward 2-D ICT processor chip for image coding

The Integer Cosine Transform (ICT) presents a performance close to Discrete Cosine Transform (DCT) with a reduced computational complexity. The ICT kernel is integer-based, so computation only requires adding and shifting operations. This work presents a parallel-pipelined architecture of an 8/spl times/8 forward two-dimensional (2-D) ICT(10,9,6,2,3,1) processor for image encoding. A fully pipelined row-column decomposition method based on two one-dimensional (1-D) ICTs and a transpose buffer based on D-type flip-flops is used. The main characteristics of 1-D ICT architecture are high throughput, parallel processing, reduced internal storage, and 100% efficiency in computational elements. The arithmetic units are distributed and are made up of adders/subtractors operating at half the frequency of the input data rate. In this transform, the truncation and rounding errors are only introduced at the final normalization stage. The normalization coefficient word length of 18-bit (13-bit effective) has been established using the requirements of IEEE standard 1180-1990 as a reference. The processor has been implemented using standard cell design methodology in 0.35-/spl mu/m CMOS technology, measures 9.3 mm/sup 2/, and contains 12.4 k gates. The maximum frequency is 300 MHz with a latency of 214 cycles (260 cycles with normalization).

The CMS trigger system

The CMS trigger system must reduce an input data rate from the LHC bunch-crossing frequency of 40 MHz to a rate which will be written to permanent storage. A detailed study has recently been made of the performance of this system. This paper presents key elements of the results obtained and gives details of a draft “trigger table” for the Level-1 Trigger and the High-Level Trigger selection at a “start-up” luminosity of 2× 1033 cm – 2s – 1. High efficiencies for most physics objects are attainable with a selection that remains inclusive and avoids detailed topological or other requirements on the event.

The Prospects for Using High-Speed Analog-to-Digital Converters to Analyze the Signals of Ionizing-Radiation Detectors

The potential advantages of recording digital signals from ionizing-radiation detectors are considered. State-of-the-art high-speed analog-to-digital converters operating at sampling frequencies of 400 MHz (2.5 ns) and higher with a buffer storage of up to 4 Gbyte and a data-input rate of up to 400 Mbyte/s are capable of recording continuous pulse sequences with a throughput of >107 pulse/s in less than 10 s. In contrast to standard recording methods in which overlapping pulses are truncated, the recording of complete signal flows allows one to detect and resolve overlapping pulses quite well, provided they arrive within ≥20–40 ns of one another.

Energy-efficient self-timed circuit design using supply voltage scaling

Energy-efficient design for self-timed circuits is investigated. Null convention logic is employed to construct speed-independent self-timed circuits. For error-free computation, the supply voltage automatically tracks the input data rate so that the supply voltage can be kept as small as possible while maintaining the speed requirement. For error-tolerable computation, such as soft digital signal processing, further energy saving is achieved at the cost of signal-to-noise ratio when an ultralow supply voltage is applied. Cadence simulation shows that 40 to 70% power can be saved by introducing −15 to −11 dB error in typical speech signal processing.

An online calorimeter trigger for removing outsiders from particle beam calibration tests

An online neural triggering system for particle identification is presented. It is developed for calibration tests with Tilecal, the hadronic calorimeter of the ATLAS experiment. The proposed neural system proves to cope with the required data input rate and achieves more than 99.7% in particle classification efficiency, even when significant particle contamination is observed in the data samples.

The muon pretrigger system of the HERA-B experiment

This paper describes the muon pretrigger system of the HERA-B experiment. The muon pretrigger is designed to detect track candidates for muons in order to generate seeds for the first level trigger (FLT) search algorithm. Muons provide the cleanest event signature in the large amount of hadronic background. In order to achieve the required precision the muon pretrigger system has to cope with an interaction rate of about 40 MHz at the HERA bunch crossing rate of 10.4 MHz. This results in a total input data rate of about 10 Gbyte/s. A total rate reduction by a factor of 200 is aimed at by the complete FLT, including the pretrigger systems (electromagnetic calorimeter, muon and high-p/sub T/), within at most 12 /spl mu/s.

LHCb base-line level-0 trigger 3D-Flow implementation

The LHCb Level-0 trigger implementation with the 3D-Flow system offers full programmability, allowing it to adapt to unexpected operating conditions and enabling new, unpredicted physics. The implementation is described in detail and refers to components and technology available today. The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on the replication of a single type of circuit of 100k gates, which communicates in six directions: bi-directional with North, East, West, and South neighbors, unidirectional from Top to Bottom, the system offers full programmability, modularity, ease of expansion and adaptation to the latest technology. A complete study of its applicability to the LHCb calorimeter triggers is presented. Full description of the input data handling, either in digital or mixed digital-analog form, of the data processing, and the transmission of results to the global level-0 trigger decision unit are provided. Any level-0 trigger algorithm (2×2, 3×3, 4×4, etc.) with up to 20 steps, can be implemented with zero dead-time, while sustaining input data rate (up to 32-bit per input channel, per bunch crossing) at 40 MHz. For each step, each 3D-Flow processor can execute up to 26 operations, inclusive of compare, ranging, finding local maxima, and efficient data exchange with neighboring channels. (One-to-one correspondence between input channel and trigger tower.) Populated with only two main types of components, front-end FPGAs and 3D-Flow processors, a single type of board, it is shown how the whole Level-0 calorimeter trigger can be accommodated into six crates (9U), each containing 16 identical boards. All 3D-Flow inter-chip Bottom to Top ports connection are all contained on the board (data are multiplexed 2 : 1, PCB traces are shorter than 6 cm); all 3D-flow inter-chip North, East, West, and South ports connections, between boards and crates, are multiplexed (8+2) : 1 and are shorter than 1.5 m. Full implementation of a 3D-Flow system, for the most complex trigger algorithm, requires 320 cables to north and south crates and 40 cables to east and west crates (Cable cost=$2 each). For applications requiring a simpler real-time algorithm (e.g., requiring less than 20 steps, which is equivalent to 10 layers of 3D-Flow processors), then the number of connections for the inter-boards (North and South), and inter-crates (East and West) will also be reduced to the number of layers used by the simpler algorithm, thus not requiring to install all cables (e.g., applications requiring only nine layers of 3D-Flow processors will save 32 cables to the North, 32 to the South, four to the East, and four to the West crates). Details are also given on timing and synchronization issues, ASIC design verification, real-time performance monitoring and design (software and hardware) development tools.

34.1: 100‐MHZ Active‐Matrix Electroluminescent Displays

AbstractAMEL displays with 12μm×12μm pixels in a 1280×1024 array have been built and operated at 100MHz input data rates. The display accepts data at 100MHz on each of the 8 parallel inputs to support a total pixel data rate of over 800 megabits per second. These high data rates were achieved using a 1.2μm effective channel length body‐tied crystalline silicon TFTs fabricated on SOI. This is the highest data rate reported for any flat panel display.

System architecture of an adaptive reconfigurable DSP computing engine

In this paper, we present the system architecture of an adaptive reconfigurable DSP computing engine for numerically intensive front-end audio/video communications. The proposed system is a massively parallel architecture that is capable of performing most low-level computationally intensive data processing including finite impulse response/infinite impulse response (FIR/IIR) filtering, subband filtering, discrete orthogonal transforms (DT), adaptive filtering, and motion estimation for the host processor in DSP applications. Since the properties of each programmed function such as parallelism and pipelinability have been fully exploited in this design, the computational speed of this computing engine can be as fast as ASIC designs that are optimized for individual specific applications. We also show that the system can be easily configured to perform multirate FIR/IIR/DT operations at negligible hardware overhead. Since the processing elements are operated at half of the input data rate, we are able to double the processing speed on-the-fly based on the same system architecture without using high-speed/full-custom circuits. The programmable/high-speed features of the proposed design make it very suitable for cost-effective video-rate DSP applications.

Two-dimensional micropipelines: for parallel-to-serialdata conversion

The two-dimensional micropipeline is introduced for data conversion between bit-parallel and bit-serial formats at a constant input data rate. By using micropipelines, the architecture has independent clock rates for the data input and output, and can be designed with level sensitive latches.

Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

The authors describe the design, integration and characterisation of a bit-level pipelined self-timed multiplier architecture. The differential structure SODS (switched-output differential structure) has been used for computation blocks and the PLCAR structure (protocol and latching controlled by acknowledge and request) for the interface blocks, introduced in an array-based architecture. A 4/spl times/4-bit multiplier has been integrated in a 1.0 /spl mu/m CMOS technology and the proposed architecture has been compared with other asynchronous approaches, showing a considerable improvement, up to 50%, in terms of area, speed and power consumption. Compared with a synchronous approach, the main advantage of the proposed architecture is a lower power consumption below a certain incoming input data rate, but at the expense of area and speed.