Data Cache Research Articles

Cache Replacement Policies

Abstract This book summarizes the landscape of cache replacement policies for CPU data caches. The emphasis is on algorithmic issues, so the authors start by defining a taxonomy that places previou...

COWCache: effective flash caching for Copy-on-Write virtual disks

Host-side flash caching emerges as an effective solution for improving the performance of virtual machines (VMs) in cloud computing environment. However, for VMs with the commonly used Copy-on-Write (COW) virtual disks, flash caching in fact has negative impacts since it brings lots of unnecessary cache writes, hurting both the VM performance and the flash endurance. This paper presents COWCache, a COW-aware caching solution that addresses this problem by co-designing flash caching with COW-based virtual disks. First, COWCache designs a new architecture that bridges the semantic gap between flash caching and virtual disk management for realizing the VMs’ real data locality. Second, it separately manages COW metadata with fine-grained caching and journaling to improve the metadata caching efficiency. Third, it provides a novel decoupled Copy-on-Write mechanism, which decouples the amplified data requests from the critical I/O path and only admits the data with real VM locality into flash cache. COWCache also introduces a new data structure, the virtual cache map, to mitigate the memory footprint overhead for indexing the cached data in flash. Evaluations show that COWCache improves the application performance by up to 122.7% and reduces the flash cache writes by up to 78.5% compared to traditional flash caching solutions.

Enabling On-the-Fly Hardware Tracing of Data Reads in Multicores

Software debugging is one of the most challenging aspects of embedded system development due to growing hardware and software complexity, limited visibility of system components, and tightening time-to-market. To find software bugs faster, developers often rely on on-chip trace modules with large buffers to capture program execution traces with minimum interference with program execution. However, the high volumes of trace data and the high cost of trace modules limit the visibility into the system operation to short program segments. This article introduces a new hardware/software technique for capturing and filtering read data value traces in multicores that enables a complete reconstruction of parallel program execution. The proposed technique exploits tracking of data reads in data caches and cache coherence protocol states to minimize the number of trace messages streamed out of the target platform to the software debugger. The effectiveness of the proposed technique is determined by analyzing the required trace port bandwidth and trace buffer sizes as a function of the data cache size and the number of processor cores. The results show that the proposed technique significantly reduces the required trace port bandwidth, from 12.2 to 73.9 times, when compared to the Nexus-like read data value tracing, thus enabling continuous on-the-fly data tracing at modest hardware cost.

Fine Granularity and Adaptive Cache Update Mechanism for Client Caching

Distributed file systems have been commonly used as the back end to provide high-performance I/O services for hosting complicated data processing, such as database workloads. By buffering the frequently used data in the local file cache, which is called the client caching mechanism, can reduce the I/O latency and improve the performance of file access. However, the overhead and complexity for ensuring data consistency may offset the performance benefits caused by data caching. This paper proposes an adaptive, per-block cache update mechanism, which can ensure data consistency of block data in a distributed file system, with low synchronization overhead. Specifically, based on the recent history of read/write requests, the proposed scheme can adaptively select the best-suited consistency update policy for each data block at run time. The experiments on database applications show that our newly proposed mechanism can greatly reduce the overhead resulted by maintaining cache consistency, especially for the workloads having fluctuating read/write ratios. As a consequence, the system performance can be also enhanced.

Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection

This work presents two fault injection and dependability test methodologies exploring the fault tolerance of successive approximation algorithms. This type of approximate computing algorithm can present an inherent fault tolerance, converging to a final correct output even under faults affecting processed data. A set of algorithms was implemented as embedded software in the ARM Cortex A9 processor of Xilinx Zynq-7000 series board. Experiments consist of exposing the decapsulated processor to laser beams targeting the data cache memory and emulation fault injections at the register file. Results show that successive approximation is effective in protecting the output from faults injected at the data cache memory, but not from the ones injected at the register file. The experiments also show that most of the silent data corruption errors provoked by data cache fault injections are not significant and can be accepted as correct by merely tolerating a result variation of as little as 1%.

Cache-Aware Computation Offloading in IoT Systems

In the Internet of Things (IoT) environment, due to the limited computing power of terminal equipment, edge-cloud computing is a good solution for sharing the computation resources. Terminals can offload partial computations to the edge servers for energy saving and reduce the data transmission delays since the edge servers are usually deployed near the terminal devices. However, in the existing solutions, there is still a lot of unnecessary data transmission when the data used in the offloading jobs of several terminals are related. Adding a shareable cache to the edge server and allowing different computing jobs to share the related data can further reduce the data transmission cost and job delay. In this paper, we study the computation offloading method with cached data and propose a novel cache-aware computation offloading strategy for edge-cloud computing in IoT. First, we formulize the cache-aware computation offloading location problem, our goal is to minimize the equivalent weighted response time of all jobs with computing power and cache capacity constraints. Then, we derive the global optimum solution based on transforming the problem to the transportation problem. Next, since the terminal device is difficult to obtain global status information, we propose an online computation offloading strategy, which is convenient in practical deployment. Finally, experiments show that our online offloading strategy approximates the global optimal solution and it reduces the weighted response time by about 26.13% on average compared to other competing algorithms.

Getting necessary historical data out of deep freeze

The changes which are brought about by natural evolution often have very long time-constants, and the data which are needed to capture and measure them can therefore span many decades, sometimes centuries. Most of the natural sciences have caches of analogue historical data that would add significantly to our understanding of the evolution of the objects in question, if only the information in those data were readily accessible in modern electronic formats. Unfortunately, many of those analogue data are in precarious physical condition and only very few have been digitized. We review briefly the global situation regarding the status of those “data at risk”, and suggest strategies that will ensure the preservation of the information that they contain, making it readily and easily accessible in the public domain for use in specific scientific research, disaster risk assessment, or citizen science projects.

OpenCache: A lightweight regional cache collaboration approach in hierarchical-named ICN

Information-centric networking (ICN) names contents instead of end-nodes and enables in-network caching to reuse those named packets, thus improving the efficiency of content delivery. On-path caching is an inherent feature in ICN, which caches contents along the path from providers to consumers, while off-path caching is not directly supported and its maintenance normally requires non-trivial overhead. In this paper, we propose a lightweight regional cache collaboration approach, called OpenCache, to sharing popular cached data among small-range caches with least cache information exchanges, especially for hierarchical-named ICN. Different from other available solutions, OpenCache enables collaborators to exchange aggregated hierarchical names (i.e., prefixes), instead of data structures summarized from separated and specific data names, to fundamentally reduce the collaborating cost of communication and maintenance. In addition, our approach exploits forwarding information base (FIB) to selectively relay Interest packets to nearby collaborative routers for low-cost data retrieval. Theoretical analyses and extensive experiments have been conducted to evaluate our scheme and the results show that OpenCache can reduce packet latency in retrieving data by about 38% compared to original ICN while its additional collaborating overhead is only around 15% of other schemes. Our approach explores the feasibility of lightweight collaboration with aggregation of hierarchical names.

Physical model of sensitive data leakage from PC-based cryptographic systems

In this paper, we present an examination of several side-channel attack scenarios on PC-based cryptosystems. Our goal was the development of a unified physical model for sensitive information leakage. The main focus of our work was electromagnetic side channels since signals with high signal-to-noise ratio (SNR) can be more conveniently captured. Moreover, the attacker can make correlations of the EM signal with other types of side-channel signals (such as voltage fluctuations and acoustic emanations). It shows that there may be a common source for a vulnerable signal that passes through several sides channels. We have simulated several attacks on targeted cryptosystems with distinct instruction sets. Trace analysis reveals empirical evidence. which corresponds to the theoretical principles of the mechanisms x86 and x64 processors. Hardware reasons for leakage come from the instructions and data in the processor cache, to be specific, from the fluctuations of power consumption, leading to changes in the voltage regulator of the processor. Thus, the fluctuations in LC circuits result in leakage on multiple side channels. In general, the obtained data together with the principles of signal formation can be used in vulnerability testing, which can examine side-channel robustness of cryptographic software on the first steps of development.

Adaptive compression method for underwater images based on perceived quality estimation

Underwater image compression is an important and essential part of an underwater image transmission system. An assessment and prediction method of effectively compressed image quality can assist the system in adjusting its compression ratio during the image compression process, thereby improving the efficiency of the image transmission system. This study first estimates the perceived quality of underwater image compression based on embedded coding compression and compressive sensing, then builds a model based on the mapping between image activity measurement (IAM) and bits per pixel and structural similarity (BPP-SSIM) curves, next obtains model parameters by linear fitting, and finally predicts the perceived quality of the image compression method based on IAM, compression ratio, and compression strategy. Experimental results show that the model can effectively fit the quality curve of underwater image compression. According to the rules of parameters in this model, the perceived quality of underwater compressed images can be estimated within a small error range. The presented method can effectively estimate the perceived quality of underwater compressed images, balance the relationship between the compression ratio and compression quality, reduce the pressure on the data cache, and thus improve the efficiency of the underwater image communication system.

Fast In-Memory Key–Value Cache System with RDMA

The quick advances of Cloud and the advent of Fog computing impose more and more critical demand for computing and data transfer of low latency onto the underlying distributed computing infrastructure. Remote direct memory access (RDMA) technology has been widely applied for its low latency of remote data access. However, RDMA gives rise to a host of challenges in accelerating in-memory key–value stores, such as direct remote memory writes, making the remote system more vulnerable. This study presents an in-memory key–value system based on RDMA, named Craftscached, which enables: (1) buffering remote memory writes into a communication cache memory to eliminate direct remote memory writes to the data memory area; (2) dividing the communication cache memory into RDMA-writable and RDMA-readable memory zones to reduce the possibility of data corruption due to stray memory writes and caching data into an RDMA-readable memory zone to improve the remote memory read performance; and (3) adopting remote out-of-place direct memory write to achieve high performance of remote read and write. Experimental results in comparison with Memcached indicate that Craftscached provides a far better performance: (1) in the case of read-intensive workloads, the data access of Craftscached is about 7–43[Formula: see text] and 18–72.4% better than those of TCP/IP-based and RDMA-based Memcached, respectively; (2) the memory utilization of small objects is more efficient with only about 3.8% memory compaction overhead.

CUE: An Intelligent Edge Computing Framework

The worldwide popularity of smart mobile devices is ushering us into the UGC era, and the UGC data explosion posts formidable challenges and insatiable demands for network bandwidth, which can be effectively handled by the emerging EC. However, the heterogeneity of EC devices and resources should be properly addressed to process UGC data in proximity to data sources. By taking UGC features and resource heterogeneity into account, we devise CUE, an intelligent EC framework based on cloud-user-edge cooperation. First, the CUE framework establishes a shared edge structure and virtualizes heterogeneous computation, storage, and communications resources. Second, a virtual resource bank (VRB) is employed to issue virtual resource coins (VRCs) for resource exchange. Finally, the processing (i.e., computation offloading) and caching of UGC data are implemented at the network edge. Remarkably, the proposed CUE framework can fully exploit the heterogeneous EC resources, protect sensitive user data, reduce network traffic load, and accommodate the UGC prosperity in the post-cloud era. To the best of our knowledge, CUE is the very first framework for heterogeneous EC resource sharing, where UGC is innovatively involved to form closed-loop VRC recycling and to support many other promising functions (e.g., trust management and VRC monetization).

Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems

Cache vulnerability due to soft errors is one of the reliability concerns in embedded systems. Dynamic reconfiguration techniques are widely studied for improving cache energy without considering the implications of cache vulnerability. Maintaining a useful data longer in the cache can be beneficial for energy improvement due to reduction in miss rates, however, longer data retention negatively impacts the vulnerability due to soft errors. This paper studies the tradeoff between energy efficiency improvement and reduction in cache vulnerability during cache reconfiguration. We propose a heuristic approach for both intertask and intratask cache reconfiguration in multitasking systems. Experimental results demonstrate that our proposed approach can significantly improve both vulnerability (25% on average) and energy efficiency (21% on average) for data cache without violating real-time constraints.

Scope-aware data cache analysis for OpenMP programs on multi-core processors

Abstract OpenMP is the de facto standard parallel programming framework on shared memory architectures, which is not only widely used in general and high-performance computing but also draws increasing interests for real-time embedded systems. Choosing the appropriate assignment of loop iterations to threads is one of the most critical decisions when parallelizing loops, especially considering the large impact by caches behaviors to the program execution time. In this paper, we study data cache analysis for OpenMP programs with parallel loops. We first present a method considering the impact of the schedule clause in OpenMP programs on cache behavior. We capture the dynamic behavior of memory access by computing its temporal scope (the loop iterations where a given memory block is accessed for a given data reference) during address analysis. Based on the ACS representation, we present a temporal scope aware data cache miss calculation technique. Through the experimental result, we propose a convenient way to choose an appropriate parallelization scheme for OpenMP programs.

Design of an Intelligent Data Cache with Replacement Policy

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

Millimeter-Wave Backhaul Traffic Minimization for CoMP Over 5G Cellular Networks

Coordinated multipoint joint transmission (JT) is a vital technique of the fifth-generation (5G) networks to increase throughput but causes a significant burden on network backhaul because the same user data must distribute to multiple base stations, called a JT cluster. Thus, many studies have explored how to reduce backhaul data traffic using caching user data at base stations. Millimeter wave (mmWave) mesh backhaul is a promising architecture for small cells to exchange cache data over 5G networks. However, this paper observes that inappropriate JT clusters and routing paths will result in unnecessary mmWave mesh backhaul bandwidth consumption such that the performance gain of the JT will be reduced. Therefore, in this paper, we study the JT clustering problem with the consideration of caches at base stations and mmWave mesh backhaul. The objective is to minimize total backhaul traffic while satisfying the data rate requirement of each user under limited radio resource units. We propose a two-stage algorithm based on dynamic programming approach to solve the problem. We prove that the dynamic programming algorithm can find an optimal solution for our subproblem. The simulation results provide several insights and show that compared with two baseline algorithms, our proposed algorithm can significantly reduce more backhaul bandwidth consumption.

ON THE CONSTRUCTION OF A SOFTWARE ARCHITECTURE FORNUCLEAR SYSTEMS ON A CRYSTAL

The article discusses how to build software architecture for multi-core systems on a chip (SoC), based on asym-metric and symmetric multiprocessing, the hypervisor. Asymmetric multiprocessing is a port for several operating systems on physi-cally separate processor cores. In symmetric multiprocessing in systems with core isolation, one OS is launched on several cores. OS SMP-system is ported without user intervention with a growing number of cores. Since all cores are managed by a single OS, message transfer between cores can occur at the L1 data cache level, providing faster communication with less jitter. Kernel isola-tion allows you to reserve a kernel for a hard real-time application, protecting it from the influence of other high-performance ker-nels, which for the software architecture allows you to select your operating system without creating low-level software when man-aging multiple operating systems. The hypervisor refers to a low-level software system. It manages several independent operating systems that are at a higher level. Developing multi-core systems-on-chip offerings focused on the embedded market are well suited for asymmetric multiprocessing configurations. This architecture is useful for developers who use the performance of a real-time operating system in combination with a diverse set of Linux kernel functions. The article discusses the software and hardware solu-tions contained in the XAPP1079 environment, which are required to run Linux on a single Zynq-7000 All Programmable system on a chip, and open source applications on the second core. Designing systems based on systems on a chip for high-performance and аreal-time applications requires an optimal solution taking into account the factors: data transfer time; separation of the operating system. A system solution for high-performance and real-time applications using a symmetric multiprocessor processing architecture with kernel isolation provides low latency, jitter and real-time system operation, while maintaining software SoC scalability. Pro-grammable logic integrated circuits containing multi-core subsystems have an efficient architecture with symmetric multiprocessing of data to ensure a compromise between the actual data transfer time and the low latency of their processing. The advantages of using symmetric multiprocessing manifest themselves if the load is distributed among several resources. In this case, the time re-quired to complete the task is reduced. However, the performance gain brought about by a simple multiplication of the number of performers will not necessarily be linear. Some tasks should be performed only sequentially. Multi-core systems are able to process packages much more efficiently than single-core ones -but only if they are managed by optimized software. It is expedient to develop multi-core computing software, including an OS with support for symmetric and asymmetric multiprocessor data processing archi-tectures, an embedded hypervisor, high-speed packet processing modules, and an exhaustive set of tools for the entire cycle of multi-core computing systems. The results of such development will find application in multiprocessor supercomputers and server applica-tions, in terminal devices, access aggregators and basic devices -where the highest throughput is required.

Adaptive probabilistic caching technique for caching networks with dynamic content popularity

This paper presents a new adaptive probabilistic cache algorithm (AProb) for modern caching networks. AProb is based on three main techniques: (1) dynamic probabilistic caching; (2) ghost list; and (3) adaptive probing and protection. It enables caching systems to quickly adjust their cached data to dynamic content popularity without intervention of network administrators and synchronization. The criteria of this adjustment are based on hit events occurring in AProb data structures. By using AProb, a caching system continuously adapts a caching probability and the ratio between probing and protection partitions of its cache. AProb has constant time complexity and its space overhead is minimal. Extensive computer simulations, which consider various network topologies and traffic traces, show that AProb offers improvement in terms of server-hit ratio, footprint distance, and caching time compared with those provided by several existing cache algorithms.

A geographic map-based middleware framework to obfuscate smart vehicles’ locations

In the 5G applications, smart vehicles typically use built-in positioning functions to query geographic map information or to access location-based multimedia or service, such as traffic image, 3D graphics or surrounding points of interest (POI) from a location-based service (LBS) provider. However, when a query is submitted, vehicles’ information such as their real locations or moving routes may be collected by the service provider. To protect vehicles’ privacy, we developed a geographic map-based middleware framework to prevent the service providers from predicting vehicles’ location or moving routes by using background information derived from the geographic maps. In addition, the middleware framework uses a caching approach to generate obfuscation areas on the maps to improve performance. The proposed method also considers popular tourist POIs on the maps to enhance the cache data hit ratio and query performance.

Cache-conscious off-line real-time scheduling for multi-core platforms: algorithms and implementation

Most schedulability analysis techniques for multi-core architectures assume a single worst-case execution time (WCET) per task, which is valid in all execution conditions. This assumption is too pessimistic for parallel applications running on multi-core architectures with local instruction or data caches, for which the WCET of a task depends on the cache contents at the beginning of its execution, itself depending on the tasks that were executed immediately before the task under study. In this paper, we propose two scheduling techniques for multi-core architectures equipped with local instruction and data caches. The two techniques schedule a parallel application modeled as a task graph, and generate a static partitioned non-preemptive schedule, that takes benefit of cache reuse between pairs of consecutive tasks. We propose an exact method, using an integer linear programming formulation, as well as a heuristic method based on list scheduling. The efficiency of the techniques is demonstrated through an implementation of these cache-conscious schedules on a real multi-core hardware: a 16-core cluster of the Kalray MPPA-256, Andey generation. We point out implementation issues that arise when implementing the schedules on this particular platform. In addition, we propose strategies to adapt the schedules to the identified implementation factors. An experimental evaluation reveals that our proposed scheduling methods significantly reduce the length of schedules as compared to cache-agnostic scheduling methods. Furthermore, our experiments show that among the identified implementation factors, shared bus contention has the most impact.