Data Flow Operations Research Articles

FlowCert: Translation Validation for Asynchronous Dataflow via Dynamic Fractional Permissions

Coarse-grained reconfigurable arrays (CGRAs) have gained attention in recent years due to their promising power efficiency compared to traditional von Neumann architectures. To program these architectures using ordinary languages such as C, a dataflow compiler must transform the original sequential, imperative program into an equivalent dataflow graph, composed of dataflow operators running in parallel. This transformation is challenging since the asynchronous nature of dataflow graphs allows out-of-order execution of operators, leading to behaviors not present in the original imperative programs. We address this challenge by developing a translation validation technique for dataflow compilers to ensure that the dataflow program has the same behavior as the original imperative program on all possible inputs and schedules of execution. We apply this method to a state-of-the-art dataflow compiler targeting the RipTide CGRA architecture. Our tool uncovers 8 compiler bugs where the compiler outputs incorrect dataflow graphs, including a data race that is otherwise hard to discover via testing. After repairing these bugs, our tool verifies the correct compilation of all programs in the RipTide benchmark suite.

Query Planning for Robust and Scalable Hybrid Network Telemetry Systems

Network telemetry systems have become hybrid combinations of state-of-the-art stream processors and modern programmable data-plane devices. However, the existing designs of such systems have not focused on ensuring that these systems are also deployable in practice, i.e., able to scale and deal with the dynamics in real-world traffic and query workloads. Unfortunately, efforts to scale these hybrid systems are hampered by severe constraints on available compute resources in the data plane (e.g., memory, ALUs). Similarly, the limited runtime programmability of existing hardware data-plane targets critically affects efforts to make these systems robust. This paper presents the design and implementation of DynaMap, a new hybrid telemetry system that is both robust and scalable. By planning for telemetry queries dynamically, DynaMap allows the remapping of stateful dataflow operators to data-plane registers at runtime. We model the problem of mapping dataflow operators to data-plane targets formally and develop a new heuristic algorithm for solving this problem. We implement our algorithm in prototype and demonstrate its feasibility with existing hardware targets based on Intel Tofino. Using traffic workloads from different real-world production networks, we show that our prototype of DynaMap improves performance on average by 1-2 orders of magnitude over state-of-the-art hybrid systems that use only static query planning.

A Streaming Data Processing Architecture Based on Lookup Tables

Processing in memory (PIM) is a new computing paradigm that stores the function values of some input modes in a lookup table (LUT) and retrieves their values when similar input modes are encountered (instead of performing online calculations), which is an effective way to save energy. In the era of the Internet of Things, the processing of massive data generated by the front-end requires low-power and real-time processing. This paper investigates an energy-efficient processing architecture based on table lookup in phase-change memory (PCM). This architecture replaces logical-based calculations with LUT lookups to minimize power consumption and operation latency. In order to improve the efficiency of table lookup, the RISC-V instruction set has included extended lookup and data stream transmission instructions. Finally, the system architecture is validated by hardware simulation, and the performance of computing the fast Fourier transform (FFT) application is evaluated. The proposed architecture effectively improves the execution efficiency and reduces the power consumption of data flow operations.

Hybrid Cloud Architecture for Higher Education System

As technology improves, several modernization efforts are taken in the process of teaching and learning. An effective education system should maintain global connectivity, federate security and deliver self-access to its services. The cloud computing services transform the current education system to an advanced one. There exist several tools and services to make teaching and learning more interesting. In the higher education system, the data flow and basic operations are almost the same. These systems need to access cloud-based applications and services for their operational advancement and flexibility. Architecting a suitable cloud-based education system will leverage all the benefits of the cloud to its stakeholders. At the same time, educational institutions want to keep their sensitive information more secure. For that, they need to maintain their on-premises data center along with the cloud infrastructure. This paper proposes an advanced, flexible and secure hybrid cloud architecture to satisfy the growing demands of an education system. By sharing the proposed cloud infrastructure among several higher educational institutions, there is a possibility to implement a common education system among organizations. Moreover, this research demonstrates how a cloud-based education architecture can utilize the advantages of the cloud resources offered by several providers in a hybrid cloud environment. In addition, a reference architecture using Amazon Web Service (AWS) is proposed to implement a common university education system.

Scalable Linear Algebra on a Relational Database System

As data analytics has become an important application for modern data management systems, a new category of data management system has appeared recently: the scalable linear algebra system. In this paper, we argue that a parallel or distributed database system is actually an excellent platform upon which to build such functionality. Most relational systems already have support for cost-based optimization-which is vital to scaling linear algebra computations-and it is well-known how to make relational systems scale. We show that by making just a few changes to a parallel/distributed relational database system, such a system can be a competitive platform for scalable linear algebra. Taken together, our results should at least raise the possibility that brand new systems designed from the ground up to support scalable linear algebra are not absolutely necessary, and that such systems could instead be built on top of existing relational technology. Our results also suggest that if scalable linear algebra is to be added to a modern dataflow platform such as Spark, they should be added on top of the system's more structured (relational) data abstractions, rather than being constructed directly on top of the system's raw dataflow operators.

Foreword to the special issue of the workshop on high performance computing systems (XVIII Simpósio em Sistemas Computacionais de Alto Desempenho, WSCAD 2017)

Foreword to the special issue of the workshop on high performance computing systems (XVIII Simpósio em Sistemas Computacionais de Alto Desempenho, WSCAD 2017)

Representations and Optimizations for Embedded Parallel Dataflow Languages

Parallel dataflow engines such as Apache Hadoop, Apache Spark, and Apache Flink are an established alternative to relational databases for modern data analysis applications. A characteristic of these systems is a scalable programming model based on distributed collections and parallel transformations expressed by means of second-order functions such as map and reduce. Notable examples are Flink’s DataSet and Spark’s RDD programming abstractions. These programming models are realized as EDSLs—domain specific languages embedded in a general-purpose host language such as Java, Scala, or Python. This approach has several advantages over traditional external DSLs such as SQL or XQuery. First, syntactic constructs from the host language (e.g., anonymous functions syntax, value definitions, and fluent syntax via method chaining) can be reused in the EDSL. This eases the learning curve for developers already familiar with the host language. Second, it allows for seamless integration of library methods written in the host language via the function parameters passed to the parallel dataflow operators. This reduces the effort for developing analytics dataflows that go beyond pure SQL and require domain-specific logic. At the same time, however, state-of-the-art parallel dataflow EDSLs exhibit a number of shortcomings. First, one of the main advantages of an external DSL such as SQL—the high-level, declarative Select-From-Where syntax—is either lost completely or mimicked in a non-standard way. Second, execution aspects such as caching, join order, and partial aggregation have to be decided by the programmer. Optimizing them automatically is very difficult due to the limited program context available in the intermediate representation of the DSL. In this article, we argue that the limitations listed above are a side effect of the adopted type-based embedding approach. As a solution, we propose an alternative EDSL design based on quotations. We present a DSL embedded in Scala and discuss its compiler pipeline, intermediate representation, and some of the enabled optimizations. We promote the algebraic type of bags in union representation as a model for distributed collections and its associated structural recursion scheme and monad as a model for parallel collection processing. At the source code level, Scala’s comprehension syntax over a bag monad can be used to encode Select-From-Where expressions in a standard way. At the intermediate representation level, maintaining comprehensions as a first-class citizen can be used to simplify the design and implementation of holistic dataflow optimizations that accommodate for nesting and control-flow. The proposed DSL design therefore reconciles the benefits of embedded parallel dataflow DSLs with the declarativity and optimization potential of external DSLs like SQL.

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

SummaryDataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems

The tremendous increase in the computing capacity of the embedded architectures has led to widespread deployment of embedded applications. These applications generally exhibit similar patterns in their specification such as filters in which multiply and accumulate operations are repetitive. If such patterns are identified and used for the system design, trade-off between the area and delay can be achieved. This paper proposes a new methodology which allows to implements a design by retrieving similar patterns known as graph isomorphs and interfaces them as HW accelerators in the system-on-chip design flow. An effective algorithm that converges in polynomial time has been proposed to find such similar subgraphs. In the next phase of the design flow, an algorithm has been proposed which performs the scheduling of clusters and minimizes the time overhead. All algorithms have been written in python for parsing the data flow description and test the correctness of the proposed work. The proposed design flow has been applied to five different programs which are sine, cosine, exponent, matrix multiplication and discrete cosine transform (DCT). These have been described as a data flow graph and have been used for results comparison. An estimation table showing the HW and SW parameter of the data flow operators has been developed for timing and area analysis of the programs. The work is an effort to show the clustering and scheduling of a standalone specification which is mapped on static reconfigurable fabric. Reconfigurable computing systems (RCS) are a popular platform for embedded computing applications as they offer a wide exploration in the design space by allowing HW, SW or HW–SW (hybrid) implementation depending on computational demand and resource requirement. These systems have inspired the designers to find new frameworks for achieving the optimized system characteristics under the given constraints. Any static or dynamic HW hardware optimization in an application can be proposed, implemented and easily verified on the chip. The results presented show the comparison of the proposed approach with SW and HW implementation of DCT design on the Xilinx ML507 board. HW timer has been used to find the execution of each implementation. The experimental verification of the proposed algorithms shows that static IP core design flow gives better results.

Explaining outputs in modern data analytics

We report on the design and implementation of a general framework for interactively explaining the outputs of modern data-parallel computations, including iterative data analytics. To produce explanations, existing works adopt a naive backward tracing approach which runs into known issues; naive backward tracing may identify: (i) too much information that is difficult to process, and (ii) not enough information to reproduce the output, which hinders the logical debugging of the program. The contribution of this work is twofold. First, we provide methods to effectively reduce the size of explanations based on the first occurrence of a record in an iterative computation. Second, we provide a general method for identifying explanations that are sufficient to reproduce the target output in arbitrary computations -- a problem for which no viable solution existed until now. We implement our approach on differential dataflow , a modern high-throughput, low-latency dataflow platform. We add a small (but extensible) set of rules to explain each of its data-parallel operators, and we implement these rules as differential dataflow operators themselves. This choice allows our implementation to inherit the performance characteristics of differential dataflow, and results in a system that efficiently computes and updates explanatory inputs even as the inputs of the reference computation change. We evaluate our system with various analytic tasks on real datasets, and we show that it produces concise explanations in tens of milliseconds, while remaining faster -- up to two orders of magnitude -- than even the best implementations that do not support explanations.

Scalable and adaptive online joins

Scalable join processing in a parallel shared-nothing environment requires a partitioning policy that evenly distributes the processing load while minimizing the size of state maintained and number of messages communicated. Previous research proposes static partitioning schemes that require statistics beforehand. In an online or streaming environment in which no statistics about the workload are known, traditional static approaches perform poorly. This paper presents a novel parallel online dataflow join operator that supports arbitrary join predicates. The proposed operator continuously adjusts itself to the data dynamics through adaptive dataflow routing and state repartitioning. The operator is resilient to data skew, maintains high throughput rates, avoids blocking behavior during state repartitioning, takes an eventual consistency approach for maintaining its local state, and behaves strongly consistently as a black-box dataflow operator. We prove that the operator ensures a constant competitive ratio 3:75 in data distribution optimality and that the cost of processing an input tuple is amortized constant, taking into account adaptivity costs. Our evaluation demonstrates that our operator outperforms the state-of-the-art static partitioning schemes in resource utilization, throughput, and execution time.

Nesting Strategies for Enabling Nimble MapReduce Dataflows for Large RDF Data

Graph and semi-structured data are usually modeled in relational processing frameworks as “thin” relations (node, edge, node) and processing such data involves a lot of join operations. Intermediate results of joins with multi-valued attributes or relationships, contain redundant subtuples due to repetition of single-valued attributes. The amount of redundant content is high for real-world multi-valued relationships in social network (millions of Twitter followers of popular celebrities) or biological (multiple references to related proteins) datasets. In MapReduce-based platforms such as Apache Hive and Pig, redundancy in intermediate results contributes avoidable costs to the overall I/O, sorting, and network transfer overhead of join-intensive workloads due to longer workflows. Consequently, providing techniques for dealing with such redundancy will enable more nimble execution of such workflows. This paper argues for the use of a nested data model for representing intermediate data concisely using nesting-aware dataflow operators that allow for lazy and partial unnesting strategies. This approach reduces the overall I/O and network footprint of a workflow by concisely representing intermediate results during most of a workflow's execution, until complete unnesting is absolutely necessary. The proposed strategies are integrated into Apache Pig and experimental evaluation over real-world and synthetic benchmark datasets confirms their superiority over relational-style MapReduce systems such as Apache Pig and Hive.

A data‐operation model based on partial vector space for batch processing in workflow

AbstractBatch processing in workflow schedules activity instances in multiple workflow cases of the same workflow type to run as a group. It can optimize business processes execution dynamically. To achieve this goal, it is necessary to define a dataflow operation language to group and ungroup the data in multiple cases of a workflow. Though our previous work has preliminarily investigated the model and its implementation, there is still lack of a formally defined model. In this paper, we first propose a method that is based on a partial vector space to model the dataflow in multiple workflow cases. Based on this model, the data operation primitives for batch processing are specified and defined formally. Since most WfMSs (Workflow Management Systems) use RDBMS (relational database management system) to store their data currently, an SQL (Structured Query Language)‐like implementation language, namely DBOL (Data Batch Operation Language), is proposed. Evaluation experiments have also been done to show its performance. Copyright © 2011 John Wiley & Sons, Ltd.

Double Input Operators of the DF KPI System

Dataflow architectures can be used advantageously for computation-oriented applications that exhibit a fine grain parallelism. The implementation of the dataflow computer architecture depends on the form of execution of the dataflow program instructions, which is implemented as a process of receiving, processing and transmission of data tokens. The architecture described in this paper belongs to a class of dynamic dataflow architectures with direct operand matching. The concept of direct operand matching represents the elimination of the costly process (in terms of computing time) related to associative searching of the operands. This process is associated with the processing units of the proposed system. The processing units are designed as a dynamic multifunction pipelined unit of five segments, Load-Fetch-Operate-Matching-Copy. This pipeline stages handle processing of operand matching of dataflow operators. From the many types of operators, this paper describes microprogram managing for double input operators.

A Parallel Prolog Abstract Machine and its Multi-Transputer Implementation

A multi-transputer implementation of PPAM-2 has been investigated in the paper. First the chosen interconnection topology of the multi-transputer-based machine is described, then the method for mapping the dataflow search graph of Prolog programs on to the chosen topology. Finally, the realisation techniques of the dataflow operations on transputers are overviewed

Automated Design of Circuits from Recursion Equations Using Theorem‐Proving Technique

AbstractThis paper aims at establishing the automated design for a circuit by the theorem‐proving technique, by formulating the circuit design as a transformation from the specification description (recursion equation) to the circuit model FN (functional network based on dataflow operation).First, rules for circuit construction and transformation rules are formulated, which are used as the inference knowledge in the theorem‐proving system. Then the circuit realization language is designed based on the modal logic, where the syntax corresponds to the FN structure, and the computation corresponds to the circuit operation. It is shown that the processing system for such a language can be realized by a technique similar to the derivation principle for the first‐order predicate logic.The theorem‐proving system for automated circuit design can be realized as a program on the circuit realization language, where the element composing the circuit is used as the declarative knowledge, and the transformation rule is used as the inference knowledge.When the design specification (recursion equation) is given as the goal clause, the automated circuit design system decides on the possibility of design, and the circuit structure information is extracted from the proof process. The behavior of the circuit can be simulated also in the process.

Process and dataflow control in distributed data-intensive systems

In dataflow architectures, each dataflow operation is typically executed on a single physical node. We are concerned with distributed data-intensive systems, in which each base (i.e., persistent) set of data has been declustered over many physical nodes to achieve load balancing. Because of large base set size, each operation is executed where the base set resides, and intermediate results are transferred between physical nodes. In such systems, each dataflow operation is typically executed on many physical nodes. Furthermore, because computations are data-dependent, we cannot know until run time which subset of the physical nodes containing a particular base set will be involved in a given dataflow operation. This uncertainty creates several problems . We examine the problems of efficient program loading, dataflow—operation activation and termination, control of data transfer among dataflow operations, and transaction commit and abort in a distributed data-intensive system. We show how these problems are interrelated, and we present a unified set of mechanisms for efficiently solving them. For some of the problems, we present several solutions and compare them quantitatively.

The Effect of Operation Scheduling on the Performance of a Data Flow Computer

The effect of incorporating a priority scheme into a data flow computer is studied in this paper. Specifically, we deal with the scheduling of instructions in a data flow program, and the mechanisms by which such scheduling may be implemented within a data flow computer. We show that the assignment of priorities to data flow operations is a special case of a problem in scheduling theory, and also belongs to the NP-complete class of problems. Therefore, we develop a heuristic approach, based on the well-known Critical Path algorithm, as a basis for determining instruction priorities. Our conclusions, based on the simulation of programs executed in a modified data flow computer, show that adding a priority mechanism is not justifiable in the general case. This is due mostly to the inability to reach the potential improvement offered by scheduling operations, because of implementation restrictions. Nevertheless, certain algorithms (e. g., DFT) can still benefit from the proposed scheme, mainly because of their highly regular, static structure.

New VLSI systolic array design for real-time digital signal processing

The well-known advantages of pipelines systolic array architecture is applied for implementation of a second-order recursive digital filter. The proposed structure achieves five-fold increase in system throughput over standard techniques, and two-fold increase over usual systolic approaches. In this letter, the data flow operation and the basic cell implementation for this design are presented.

EPILOG = PROLOG + Data Flow

Spurred by the desire to construct multi- processor computer architectures, researchers have been proposing alternatives to the conventional wisdom of the Von Neumann design. One of the most Interesting and innovative of these is the class of machines based on the principle of data-flow - the order in which data-flow operations are executed is dependent solely on the availability of input data. The results of experiments with both real and simulated data-flow computers have, however, been rather less than earth shattering. It is the thesis of this work that PROLOG contains within it the seeds of a solution for the difficulties found in data-flow.The material contained in this work is a revision and substantial expansion of sections 2 and 3 of [Wise 82].