Dataflow Computation Research Articles

Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

A Taylor expansion diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from an HDL design specification and discusses the application of TEDs in proving the equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for dataflow design verification. Application of TEDs to algorithmic and behavioral verification is demonstrated

COMPLEXITY OF BIO-COMPUTATION: SYMBOLIC DYNAMICS IN MEMBRANE SYSTEMS

We discuss aspects of biological relevance to the modelling of bio-computation in a multiset rewriting system context: turnover, robustness against perturbations, and the dataflow programming paradigm. The systems under consideration are maximally parallel and asynchronous parallel membrane systems, the latter corresponding to computation in which the notion of time is operationally meaningless. A natural geometrical setting which seems promising for the study of computational processes in general multiset rewriting systems is presented. Configuration space corresponds to a subset of the lattice [Formula: see text], d ∈ N, and state transitions correspond to vector addition. The similarities and differences with Vector Addition Systems and Petri nets are discussed. Symbolic dynamics are introduced on special partitions of configuration space and we indicate different notions of complexity for membrane systems based on this and related concepts such as graph complexity and minimal automata. Some examples of synchronized, pipelined dataflow computations are given and decompositions into functional subunits are briefly commented on.

Test Selection Strategies for Lustre Descriptions in GATeL

We describe various test selection techniques from Lustre descriptions using the tool GATeL. The Lustre language is declarative and describes synchronous data-flow computations. Our test generation tool interprets the language constructs as boolean and integer interval constraints. Test sequence generation is automated using constraint logic programming techniques. GATeL provides various mechanisms to allow testers to define their own selection strategies. They are illustrated on an simple example.

Intensional and Extensional Semantics of Dataflow Programs

Abstract. We compare two semantic models of dataflow programs: a synchronous version of the classical Kahn semantics, and a new semantics in a category of synchronous processes. We consider the Kahn semantics to be extensional, as it describes the functions computed by dataflow nodes, and the categorical semantics to be intensional, as it describes the step-by-step production of output tokens from input tokens. Assuming that programs satisfy Wadge’s cycle sum condition and are therefore deadlock-free, we prove that the two semantics are equivalent. This equivalence result amounts to a proof that function composition in the extensional semantics is faithfully modelled by the detailed interactions of the intensional semantics, and provides further insight into the nature of dataflow computation.

Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs)

This paper presents a new design that implements the data-driven (i.e. dataflow) computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle (as is the case for control-flow CPUs), instructions in dataflow computers enter the execution unit on their own when they are ready to execute. This way, the application-knowledgeable algorithm, rather than the application-ignorant CPU, is in control. This approach could eventually result in outstanding performance and elimination of large numbers of redundant operations that plague current control-flow designs. Control-flow and dataflow machines are two extreme computation paradigms. In their pure form, the former machines follow an inherently sequential execution process while the latter are parallel in nature. The sequential nature of control-flow machines makes them relatively easy to implement compared to dataflow machines, which have to address a number of issues that are easily solved in the realm of the control-flow paradigm. Our dataflow design solves these issues at the intelligent memory level, separating the processor from dataflow maintenance tasks. It is shown that using intelligent memories with basic components similar to those of FPGAs produces a feasible approach. Expected improvements within the next few years in underlying intelligent memory and FPGA technologies will have the potential to make the effect of our approach even more dramatic.

A dataflow computer which accelerates execution of sequential programs by precedent firing instructions

AbstractIn the dataflow machine, it is important to avoid degradation of performance in sequential processing, and it is important from the viewpoint of hardware scale to reduce the number of waiting operands. This paper demonstrates that processing performance is degraded by sequential processing in the switching process, and presents a method of remedy. Precedent firing control is proposed as a means of remedy, and it is shown by a simulation that the execution time and the total number of waiting operands can be reduced by the precedent firing control. Then the hardware scale is examined as an evaluation of precedent firing control. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(9): 68–77, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.1153

Improving Software Performance with Configurable Logic

We examine the energy and performance benefits that can be obtained by re-mapping frequently executed loops from a microprocessor to reconfigurable logic. We present a design flow that finds critical software loops automatically and manually re-implements these inconfigurable logic by implementing them in SA-C, a C language variation supportinga dataflow computation model and designed to specify and map DSP applicationsonto reconfigurable logic. We apply this design flow on several examples fromthe MediaBench benchmark suite and report the energy and performance improvements.

Non-coding RNAs: the architects of eukaryotic complexity.

Around 98% of all transcriptional output in humans is non-coding RNA. RNA-mediated gene regulation is widespread in higher eukaryotes and complex genetic phenomena like RNA interference, co-suppression, transgene silencing, imprinting, methylation, and possibly position-effect variegation and transvection, all involve intersecting pathways based on or connected to RNA signaling. I suggest that the central dogma is incomplete, and that intronic and other non-coding RNAs have evolved to comprise a second tier of gene expression in eukaryotes, which enables the integration and networking of complex suites of gene activity. Although proteins are the fundamental effectors of cellular function, the basis of eukaryotic complexity and phenotypic variation may lie primarily in a control architecture composed of a highly parallel system of trans-acting RNAs that relay state information required for the coordination and modulation of gene expression, via chromatin remodeling, RNA-DNA, RNA-RNA and RNA-protein interactions. This system has interesting and perhaps informative analogies with small world networks and dataflow computing.

Nondeterministic dynamic programming on a parallel coprocessing system

We describe how nondeterministic dynamic programming (DP) algorithms can be designed for a new class of parallel coprocessing systems using “functional memory”, an architecture based upon dataflow computer principles. We also show how Petri nets can be used to model and express such parallel DP algorithms. Finally, we discuss architectural improvements that would facilitate the processing of Petri net models of nondeterministic DP algorithms on functional memory computers (FMC).

Employing data flow testing on object-oriented classes

At the class testing level, state-based testing and data flow testing techniques have been employed. However, while the former only involves the variables that have an effect on the behaviour of the object under test, it is possible for errors to occur in variables, which do not define an object’s state. Data flow testing has been applied to generate test cases for testing classes using data flow criteria, but this is a difficult task. Moreover, some of data flow test cases thus generated may be unworkable. Selecting data flow test cases based on sequences of specification messages is a way to reduce the effort of generating feasible intra-class data flow test cases. However, some test cases cannot be selected, if data flow anomalies exist within the sequences. The data flow testing technique in this research is divided into two stages; first detecting data flow anomalies and then computing data flow test cases.

Evaluation of Neural and Genetic Algorithms for Synthesizing Parallel Storage Schemes

Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at runtime.(1, 2) Allocating the data structure(1) to separate memories whenever the data may be accessed in parallel allows improvements in memory access time of 13 to 40%. We are concerned with synthesizing compiler storage schemes for minimizing array access conflicts in parallel memories for a set of compiler predicted data access patterns. The access patterns can be easily found for many synchronous dataflow computations like multimedia compression/decompression algorithms, DSP, vision, robotics, etc. A storage scheme is a mapping from array addresses into storages. Finding a conflict-free storage scheme for a set of data patterns is NP-complete. This problem is reduceable to weighted graph coloring. Optimizing the storage scheme is investigated by using constructive heuristics, neural methods, and genetic algorithms. The details of implementation of these different approaches are presented. Using realistic data patterns, simulation shows that memory utilization of 80% or higher can be achieved in the case of 20 data patterns over up to 256 parallel memories, i.e., a scalable parallel memory. The neural approach was relatively very fast in producing reasonably good solutions even in the case of large problem sizes. Convergence of proposed neural algorithm seems to be only slightly dependent on problem size. Genetic algorithms are recommended for advanced compiler optimization especially for large problem sizes; and applications which are compiled once and run many times over different data sets. The solutions presented are also useful for other optimization problems.

Optimizing computations for effective block-processing

Block-processing can decrease the time and power required to perform any given computation by simultaneously processing multiple samples of input data. The effectiveness of block-processing can be severely limited, however, if the delays in the dataflow graph of the computation are placed suboptimally. In this paper we investigate the application of retiming for improving the effectiveness of block-processing in computations. In particular, we consider the k-delay problem : Given a computation dataflow graph and a positive integer k , we wish to compute a retimed computation graph in which the original delays have been relocated so that k data samples can be processed simultaneously and fully regularly. We give an exact integer linear programming formulation for the k -delay problem. We also describe an algorithm that solves the k -delay problem fast in practice by relying on a set of necessary conditions to prune the search space. Experimental results with synthetic and random benchmarks demonstrate the performance improvements achievable by block-processing and the efficiency of our algorithm.

Evolution-Based Scheduling of Computations and Communications on Distributed-Memory Multicomputers

We present a compiler optimization approach that uses the simulated evolution (SE) paradigm to enhance the finish time of heuristically scheduled computations with communications. This is especially beneficial to the class of synchronous dataflow computations which are generally compiled once and run many times over different data sets. Unlike genetic approaches which generally use task swapping to create differential variations, our approach consists of adding pseudo-edges to the task graph to guide the scheduler in the alignment and clustering of dominant tasks. Added edges alter only the task graph without modifying the scheduler, which provides useful flexibility in the implementation of compiler optimization options. The intelligence of iterative methods is used by SE to reduce the run-time and to avoid local minima by using the hill-climbing property of search-based methods. Evaluation is carried out on a wide variety of computation graphs which are studied for different levels of communication granularities and task parallelisms. A statistical analysis of results shows that edge-addition SE is capable of finding near-optimum schedules as well as outperforming other known heuristics such as ETF, DLS and GLS. Moreover, this approach is useful in complementing heuristics whose solution finish time cannot be guaranteed for arbitrary communication and parallelism. Since the performance of most scheduling heuristics is profile-sensitive, optimizing the heuristic solutions through edge-addition SE provides increased confidence in the quality of the solution.

A new graduate course on optical computing

A new optical computing course offered at the graduate level is described. The term "optical computing" used here refers to the design of digital computer system modules and interconnections using optical/optoelectronic technologies. The course has been offered in the College of Computer Science and Engineering (CCSE), by both the computer engineering (COE) and the information and computer science (ICS) departments while the author was at King Fahd University of Petroleum and Minerals (KFUPM). In essence, the course was intended for a wide audience. Students from other disciplines, such as electrical engineering (EE) and systems engineering (SE), can register for the course as an elective. The course main topics are: motivation and background for optical computing; subsystems for optical computing that discusses the different types of optical interconnection networks, optical memory, optical arithmetic/matrix computations and related algorithms; and architectural models of computations where optical LANs/MANs, optical dataflow computers, optical cellular automata, and optical neural networks are discussed.

Parametric Simulation Of A Dataflow Performance Model

Conventional performance evaluation models for multiprocessor systems cannot be directly applied to express the behavior of a dataflow computer architecture because of the different characteristics of the architectures. The conventional performance models do not take into account all the important architectural characteristics in formulating the performance of the target systems. Even though some queuing models have been proposed for the performance evaluation of the dataflow computers, they do not include such important performance factors as firing rules, organization of processing elements, and thread-scheduling overheads. The authors propose a novel performance evaluation model based on dataflow semantics, and present the simulation results using the parametric values of the important performance factors. The proposed model not only offers solutions for most problems appearing in the conventional performance evaluation models, but also provides more expressive power than the previous ones.

Program slicing based on data-flow computation of path dependence flow graphs

Program slicing is a technique to extract from a program a set of statements (referred to as a slice) that have certain properties; such techniques are widely used, for example, for simplification and maintenance of software. This paper proposes a particular method to generate a slice that is formally represented by using a path dependence flow graph (PDFG), namely, by means of interpretive execution of the PDFG based on data-flow computation (1). Since the proposed method is a generalization of the conventional method of interpretive execution of PDFG based on data-flow computation, the same scheme of computation control can be employed as is used in other techniques of PDFG analysis, for example, infeasible path detection (2). The slicing algorithm is specified for nodes in the form of local rules. Therefore, by partially modifying those rules, new varieties of slices can be easily obtained, for example, more precise slices (3). During firing control in data-flow computation, executable nodes are found, and slice is generated simply by consecutive execution of rules at those nodes, which implies simple computation control (4). Since control of slicing can be distributed among nodes, parallel processing is possible (5). A generalized method that offers generation of slices not obtainable by conventional methods is proposed. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 22–33, 1997

Development, Analysis, and Verification of a Parallel Hybrid Dataflow Computer Architectural Framework and Associated Load-Balancing Strategies and Algorithms via Parallel Simulation

This paper first presents the requirements for and the architectural framework of a type of real-time parallel dataflow computer architecture, specifically, a Hybrid Data/Command Driven Architecture (HDCA). Application of such an architecture is discussed. Goals, strategies, and algorithms for both static load-balancing and dynamic resource allocation on an HDCA system are presented. A parallel simulation of an HDCA system employing the presented static load-balancing and dynamic resource allocation algorithms is developed and presented. The parallel simulation was executed on a parallel computer system for increased fidelity. Analysis of simulation results for two example applications of the architecture allowed verification of design goals and correct performance of the HDCA architectural framework and associated static load-balancing and dynamic resource allocation strategies and algorithms.

Massively Parallel Dataflow Computer Dedicated to Real-Time Image Processing

This paper describes a massively parallel dataflow computer dedicated to real-time image processing. Two types of data-driven processing elements are embedded into a regular cubic mesh: 1024 low level custom dataflow processors (50Mops/s each) and 36

Partitioning and scheduling to counteract overhead

We introduce a scheduling model, inspired by data flow computers, in which the overhead incurred in a system as well as computation time are described explicitly. Using this model, we provide algorithms for partitioning programs so as to minimize their completion time. In the traditional data flow paradigm, every instruction is considered a ‘task’, and it is scheduled for execution as early as possible. Implementations of this scheme, however, involve overheads which affect the running time of the programs. We propose to partition the program into larger grains, each containing one or more instructions, such that scheduling those grains would result in minimizing the completion time. Our model accounts for both the overhead incurred when executing a program and the actual execution time of its instructions. Within this framework we derive lower and upper bounds on the execution time of programs represented as trees and DAGs. We provide algorithms for optimally partitioning such programs when there are enough execution units. The algorithms have time complexity O(¦V¦ 2) and O(¦V¦ 5) for trees and DAGs, respectively (where ¦V¦ is the number of nodes). In the case of a limited number of execution units, we show that the algorithm for trees approximates the best solution with a ratio of 4. Using the same proof techniques we show sufficient conditions for approximating the problem for DAGs, noting that approximation is the best that can be sought for as the problem is NP-complete. The scheduling problem solved is general, and its solution can also be used for scheduling problems which have been studied before outside the data flow paradigm. Some of the results are also applicable to existing data flow machines, and to simulations of data flow programs on other machines.

Article summaries

The dataflow model of computation, particularly the recent trend in combining dataflow processing with control flow processing, provides attractive alternatives for designing new computer architectures. This marriage has also motivated researchers to analyze how to apply the familiar concepts within the framework of this new architectural model. The concept of cache memory has proven its effectiveness in the traditional control flow architecture because of the spatial and temporal localities that govern the organization of the conventional programming environment. Therefore, the authors investigate the presence of localities in dataflow programs and analyze whether the cache can be incorporated into dataflow architectures. Addressing the application of cache memory in the dataflow environment, the authors compare the control flow and dataflow programming environments, address previous work to incorporate cache in the dataflow computation, and discuss how to improve and detect locality in a dataflow program.