Wide Data Bus Research Articles

Trans_Proc

A reconfigurable transform processor is proposed and implemented here. Firstly, a brief study of processors implementing different transformations is presented. We have categorized the transform processor as the one which can implement a number of linear transforms using reconfigurability. The theoretical suitability regarding the architecture of the processor is proved by graph theory method. Then the complete architecture of the overall processor and the processing element is presented and implemented using VHDL. The complete instruction set suitable to the processor is designed. The instructions are mapped to the sequence of control signals. Generating sequence of control signals for every type of instructions would finally create a hardwired control unit for the processor which was also presented. Next the processor is fed with data to simulate it. A three-phase simulation is carried out to prove the correctness of the design. Finally the same processor with a data bus width of 32 to 512 is implemented and compared in terms of speed and size.

A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus

A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus

High-performance version of the RPB code based on graphic processors for determination of the plasma boundary in tokamaks

The operation of modern tokamaks is impossible without an effective system for controlling the plasma boundary during the discharge. In this paper, we consider a method for determining the plasma boundary on the basis of integral equations. A high-speed parallel code using GPUs was developed for this purpose. Different methods of parallelization of the algorithm have been considered. The possibility of processing the magnetic measurements in real time during experiments is shown. The effect of the technical parameters of GPUs (the number of cores, the data bus width, the amount of internal memory) on the performance is also shown. The simulation results for the T-15MD tokamak, currently under construction at National Research Center Kurchatov Institute, are presented.

Forming and Co-simulation of Square and Triangular Waveforms by Using System Generator

Nowadays Field Programmable Gate Arrays(FPGAs) are used to implement several processes in different areas such military defense, medical devices, automation, telecommunication, and image processing etc. Some of the advantages of FPGA are parallel and hardware processing. On the other hand programming FPGAs by classic design methodologies requires much effort. Therefore, design tools like System Generator can provide facilities about programming FPGAs. System Generator is a design tool from Xilinx to program the Xilinx FPGAs in MATLAB/Simulink graphic based editor. Also its block set is limited with respect to Simulink, has. In this study square, and triangular waveforms are built with the basic blocks of System Generator tool. These waveforms belong to basic sources for signal processing. Generally, they are used in power electronics especially for producing PWM, or sinus PWM. Also co-simulation can be done by using System Generator. Square waveform block, which is implemented, has variable amplitude, frequency, duty cycle, and offset values whereas triangular waveform has variable amplitude, frequency, and offset values. Triangular waveform has an error as 2 % due to data bus width.

Fast Transaction-Level Model for Direct Memory Access Controller

Transaction-Level Modeling (TLM) has been widely used in system-level design in the past few years. Simulation speed of Virtual Platforms (VPs) depends mainly on the transactions which are initiated by the Programmer’s View (PV) models of the VP devices. PV models are required to run at highest simulation speed. Data bus width as a hardware (HW) parameter should not reduce simulation speed of the modeled transactions. Furthermore, HW-related parameters should only be accounted for when considering timing of the models. A fast SystemC-TLM model is developed for the widely used ARM PrimeCell PL080 DMAC IP. The performance of the proposed model is validated against a developed RTL model for the same device. The effect of the transactions granularity on simulation speed is determined. Different programmed transfers are simulated and compared with open-source Quick Emulator (QEMU)-based models. The developed model is compared with the developed RTL, the open-source QEMU model, and the existing ARM Fast Model (AFM). It is shown that simulation time of the developed model is reduced by two orders of magnitude as compared to the other existing models.

IBEX: Versatile Readout ASIC With Spectral Imaging Capability and High Count Rate Capability

IBEX is a novel mixed-mode CMOS application-specific integrated circuit (ASIC), developed at DECTRIS Ltd., dedicated to the readout of hybrid photon counting semiconductor pixel detectors. The chip has been strictly designed in a radiation tolerant enclosed transistor layout and is fabricated in a 110-nm CMOS technology with eight metal layers. It consists of a $256\times 256$ matrix of $75\times 75\,\,\mu \text {m}^{2}$ pixels, which results in an overall chip size of $19.27\times 19.76$ mm2 with periphery, supply, and I/O pads included. A so-called merging mode allows for an increased pixel size of $150\times 150\,\,\mu \text {m}^{2}$ . The pixel readout electronics supports electrons and holes collection, and consists of a charge sensitive preamplifier with programmable gain, a shaper, and two comparators that allow for two independent energy thresholds. In the merging mode, the number of energy thresholds is increased up to four. In order to minimize the pixel-to-pixel energy threshold variation, each pixel comparator can be adjusted with a 6-bit trim digital-to-analog converter. The ASIC can operate in a continuous readout mode with two independent 16-bit counters or in a high counting range mode with a single 32-bit counter per energy threshold level. The chip features counter overflow handling and an instant retrigger technology with an adjustable retrigger time for a significantly improved high-rate counting performance. The ASIC offers a selectable external data bus width of 4, 8, or 16-bit. The count rate limit of the readout chip dc-coupled with a silicon sensor lies at around 10 Mcts/s/pix. The measurements show an electronic pixel noise of $89\,\,e^{-}$ rms and the detectable photon energy range between 3 and 160 keV.

Performance Costs of Software Cryptography in Securing New-Generation Internet of Energy Endpoint Devices

In past years, cryptography has been considered a difficult task to achieve on sensor nodes for the Internet of Energy (IoE) owing to the resource-constrained nature of 8- and 16-bit microcontroller units (MCUs). Previous attempts at implementing cryptographic services on wireless sensor nodes have resulted in high power consumptions, long operating times, and the depletion of memory resources. Over the last decade, however, processors for the IoT and IoE have improved; with increased operating power and memory resources, longer data bus widths and low-power consumption. With the improvements made to processors suitable for building IoT devices, the question remains whether endpoint nodes should still be considered capable of only supporting the most lightweight of cryptographic mechanisms. We evaluate the capabilities of a device family (Cortex-M series processors) commonly found in programmable logic controllers to implement standard, verified software cryptographic libraries in terms of execution times, memory occupation, and power consumption in order to determine their adequacy for use in smart grid applications. It was seen that the MCUs were easily capable of running standard cryptographic algorithms. However, the use of public key cryptography may still require the inclusion of a hardware crypto accelerator or the use of a secure MCU implementing public key cryptography; as the relatively long execution times seen during the operation of ECDSA, for example, could be intolerable within a real time IoE application.

Efficient Computerized-Tomography Reconstruction Using Low-Cost FPGA-DSP Chip

In this paper, filtered back-projection algorithm is optimally implemented using low-cost Spartan 3A-DSP 3400 chip. The optimization enables parallel implementation. The combination of the pixel parallelism and projection parallelism is presented to significantly reduce the total reconstruction time to produce the image. The applied data is presented in fixed point format to achieve efficient implementation with maximum speed. The selection of data bus-width is optimized with very little error and good visual quality required for medical images. Before implementation, the computer tomography ( CT ) reconstruction simulator is developed to provide a testing reference for the hardware implementation. Using the combination of the pixel parallelism and projection parallelism, the presented hardware design achieves image reconstruction of a 512-by-512 pixel image from 1024 projections in 134. 8ms using 50 MHz clock cycles. It achieves the reduction of the required number of clock cycles to form an image from projections by 60 % comparing to the state of the art of the reconstruction time using field programmable gate array ( FPGA ) design.

Performance evaluation of SD – cards by "system-on-chip" technology

Subject matter. We propose the hardware and software block for performing write or read operation and testing the performance of different SD-cards using the technology of "system-on-chip" in integrated environment by Altera. This task is relevant for the design of high-performance parallel systems on a chip, where the lower limit for writing speed (and/or reading) is critical and significant. Method. The proposed approach is based on three items. First, schemes are used with programmable logic to create a compact hardware and software unit as part of video system on chip. Secondly, reprogrammable structures are applied that support serial and parallel modes of exchange. Thirdly, the increment of data bus width is possible, via the serial transfer and the parallel connection of multiple units simultaneously. Main Results. The analysis of test results of different memory cards has shown that the speed of writing and reading for all cards differs from the declared one by manufacturer, and the error rate of writing (and reading) of data is 30...50% (for reading ~30%). A maximum download speed of memory cards is possible by increasing the number of cascade-connected blocks. The results show that the simplest implementation of this hardware-software unit requires resources of the order of 2000-2500 elementary logic cells. Each cell implements the logical operation "AND-OR with memory", while the resource ЕР3С25F256C8 of the popular chip family Cyclone III consists of 5976 (26%) of these cells with the chip price equal to $5-10 apiece. Practical Relevance. The authors believe that the proposed hardware-software unit can be regarded as the cheapest specialized component in the ECB domestic microelectronics industry to create video information in real time systems.

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The experimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional bus for multicore applications using a 64-bit wide data bus in 45 nm technology.

A Low Complexity-High Throughput QC-LDPC Encoder

This paper introduces hardware architectures for encoding Quasi-Cyclic Low-Density Parity Check (QC-LDPC) codes. The proposed encoders are based on appropriate factorization and subsequent compression of involved matrices by means of a novel technique, which exploits features of recursively-constructed QC-LDPC codes. The particular approach derives to linear encoding time complexity and requires a constant number of clock cycles for the computation of parity bits for all the constructed codes of various lengths that stem from a common base matrix. The proposed architectures are flexible, as they are parameterized and can support multiple code rates and codes of different lengths simply by appropriate initialization of memories and determination of data bus widths. Implementation results show that the proposed encoding technique is more efficient for some LDPC codes than previously proposed solutions. Both serial and parallel architectures are proposed. Hardware instantiations of the proposed serial encoders demonstrate high throughput with low area complexity for code words of many thousand bits, achieving area reduction compared to prior art. Furthermore, parallelization is shown to efficiently support multi-Gbps solutions at the cost of moderate area increase. The proposed encoders are shown to outperform the current state-of-the-art in terms of throughput-area-ratio and area-time complexity by 10 to up to 80 times for codes of comparable error-correction strength.

Performance Evaluation for Field Programmable Gate Array-based Bioinformatics Sequence Alignment

Sequence alignment is a computationally expensive activity in bioinformatics that can benefit significantly from Field Programmable Gate Array-based high-performance computing systems. This paper evaluates the performance of such systems for bioinformatics sequence alignment applications considering various parameters like data bus width (W), the number of processing elements, and the maximum operating frequency.

Research and Application of a FPGA-Based Dynamic Distributed Algorithm

A dynamic distributed algorithm (DDA) with a look-up dynamic table instead of ROM was put forward based on the theory of signed distributed algorithm, in order to improve processing speed and flexibility of product sum on FPGA. Since the DDA occupies few hardware resources, performs fast operation and realizes programmable coefficient, the limitation of digital signal processing speed on fixed data bus width and sequential operation was avoided by using the algorithm. At the same time, an effective solution to realizing coefficient programmable FIR filter was presented.

Silicon Nanowire Transistors for Implementing an Field Programmable Gate Array Architecture with Scan Chain

This study presents a Field Programmable Gate Array (FPGA) architecture that uses vertical, undoped silicon nanowire transistors with metal gates and utilizes scan chain approach to minimize wiring channels. The study starts with a brief description of the nanowire transistor, its SPICE model with RC parasitics, and continues with an in-depth analysis of circuit performance and power dissipation of CMOS nano-circuits used in this particular FPGA architecture. The device design cycle optimizes both the NMOS and PMOS nanowire transistors for minimal dynamic power dissipation. Each transistor is modeled using BSIMSOI; parasitic resistance and capacitance values are extracted for SPICE simulations. FPGA is composed of cluster blocks, each of which contains three 4-input Look-Up-Tables (4-LUT). Each 4-LUT can be programmed to implement either combinatorial logic or state machine. Scan chains are used to program a specific logic function for each 4-LUT, to define data-paths in a cluster and between clusters and to reduce wiring channels. Inter-cluster communication is established by an 8-bit wide data bus and 4 shared switch boxes placed at each corner of a cluster. Worst-case propagation delay for a 4-LUT is 20.8 ps from its clock input to its output; the worst-case inter-cluster wire delay is 4.8 ps between 2 diagonally adjacent clusters and 11.2 ps between 2 diagonal clusters placed at 4 cluster lengths away. Worst-case dynamic power dissipation of a 4-LUT is 2.8 μW if there is no overlap between selector inputs to a 4-LUT and increases by 60 nW/ns of overlap at 10 GHz. FPGA layout contains silicon nanowire transistors placed in a fabric matrix where each NMOS (PMOS) transistor has 4 neighboring PMOS (NMOS) transistors and occupies approximately 0.16 cm 2 .

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration

Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.

Byte access method for wide data bus memory based on FPGA

It is a widely accepted approach to use wide data bus to increase the data accessing speed.However,this method causes the inconvenience on reading and writing data in bytes.The common operation mechanism of current mainstream SDRAM memory chip was analyzed,and a new byte alignment method was proposed for the SDRAM controller.Based on the given byte-address and input data,the new method could generate correct address and byte control signals,also aligned the bytes to the corresponding positions.The architecture and processing flow were illustrated in detail,as well as the implementation on Field Programmable Gate Array(FPGA) chips.Compared with other schemes based on memory cache and twice-memory-access,this method costs fewer hardware resources and memory bandwidth.

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.

Estimating data bus size for custom processors in embedded systems

We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.

Byte and Modulo Addressable Parallel Memory Architecture for Video Coding

This paper proposes an internal data memory architecture supporting byte and modulo addressing for processors having subword parallel processing capability, or alternatively, multiple SIMD-connected processing elements on-chip. Byte-addressable memory efficiently relieves the data word alignment problem in motion estimation block matching. In addition, a special modulo addressing allows part of the bytes in a word to be accessed simultaneously from the both ends of a circular buffer. With the modulo-addressable memory, the external memory bandwidth can be significantly reduced, while preserving efficient memory access performance in block-matching operations. The proposed data memory architecture consists of parallel memory modules, address computation circuitry, and data permutation network. Designs for different data bus widths (N= 2, 4, 8 bytes) are considered.

Scalable Parallel Memory Architectures for Video Coding

Current video compression standards, which process frames macroblock by macroblock, employ several processing functions to achieve the compression. These functions refer to data memory address space in different ways. E.g., performing motion estimation and motion compensation functions requires many times data accesses unaligned to word boundaries. On the other hand, Discrete Cosine Transformation (DCT) and inverse of it (IDCT) for 8 × 8 block can be performed first for rows and then for columns. Thus, transposition is needed between these two stages. Among other things, parallel memory architecture can provide a solution for these tasks. In our other paper, we shortly surveyed parallel memory architectures and proposed parallel memory architecture designs for different data path widths for video coding applications. In this paper, we construct video coding function examples by using the proposed parallel data memory efficiently. Furthermore, performance and implementation cost of the parallel memory architecture are estimated and compared to more conventional memory architectures. The examples are given for different data bus widths (16, 32, 64, and 128 bits). We show that the parallel memory can keep the data path fully utilized in many video coding function implementations. This ensures high-speed operation and full utilization of the processing resources.