IBEX: Versatile Readout ASIC With Spectral Imaging Capability and High Count Rate Capability

Abstract

IBEX is a novel mixed-mode CMOS application-specific integrated circuit (ASIC), developed at DECTRIS Ltd., dedicated to the readout of hybrid photon counting semiconductor pixel detectors. The chip has been strictly designed in a radiation tolerant enclosed transistor layout and is fabricated in a 110-nm CMOS technology with eight metal layers. It consists of a $256\times 256$ matrix of $75\times 75\,\,\mu \text {m}^{2}$ pixels, which results in an overall chip size of $19.27\times 19.76$ mm2 with periphery, supply, and I/O pads included. A so-called merging mode allows for an increased pixel size of $150\times 150\,\,\mu \text {m}^{2}$ . The pixel readout electronics supports electrons and holes collection, and consists of a charge sensitive preamplifier with programmable gain, a shaper, and two comparators that allow for two independent energy thresholds. In the merging mode, the number of energy thresholds is increased up to four. In order to minimize the pixel-to-pixel energy threshold variation, each pixel comparator can be adjusted with a 6-bit trim digital-to-analog converter. The ASIC can operate in a continuous readout mode with two independent 16-bit counters or in a high counting range mode with a single 32-bit counter per energy threshold level. The chip features counter overflow handling and an instant retrigger technology with an adjustable retrigger time for a significantly improved high-rate counting performance. The ASIC offers a selectable external data bus width of 4, 8, or 16-bit. The count rate limit of the readout chip dc-coupled with a silicon sensor lies at around 10 Mcts/s/pix. The measurements show an electronic pixel noise of $89\,\,e^{-}$ rms and the detectable photon energy range between 3 and 160 keV.