Cyclic Redundancy Research Articles

Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA

Advances in quantum computing have urged the need for cryptographic algorithms that are low-power, low-energy, and secure against attacks that can be potentially enabled. For this post-quantum age, different solutions have been studied. Code-based cryptography is one feasible solution whose hardware architectures have become the focus of research in the NIST standardization process and has been advanced to the final round (to be concluded by 2022–2024). Nevertheless, although these constructions, e.g., McEliece and Niederreiter public key cryptography, have strong error correction properties, previous studies have proved the vulnerability of their hardware implementations against faults product of the environment and intentional faults, i.e., differential fault analysis. It is previously shown that depending on the codes used, i.e., classical or reduced (using either quasi-dyadic Goppa codes or quasi-cyclic alternant codes), flaws in error detection could be observed. In this work, efficient fault detection constructions are proposed for the first time to account for such shortcomings. Such schemes are based on regular parity, interleaved parity, and two different cyclic redundancy checks (CRC), i.e., CRC-2 and CRC-8. Without losing the generality, we experiment on the McEliece variant, noting that the presented schemes can be used for other code-based cryptosystems. We perform error detection capability assessments and implementations on field-programmable gate array Kintex-7 device xc7k70tfbv676-1 to verify the practicality of the presented approaches. To demonstrate the appropriateness for constrained embedded systems, the performance degradation and overheads of the presented schemes are assessed.

Quantitative assessment of crop residues in no-till technology according to remote sensing data and field soil cover survey

The key feature of the no-till technology is the preservation of crop residues on the soil surface. Crop residues quantitative assessment is an important task when introducing technology into production. On the basis of field and remote sensing data, different approaches to this assessment are considered. The research was carried out in the Budennovsky district of the Stavropol Territory in the fields of farms using both traditional technology (TT) and no-till (ПП). Images of the Sentinel-2 system were used as remote sensing data, on the basis of which the spectral indices NDTI and NDVI were calculated. Three methods were used to estimate the projective cover by plant residues: 1) weight accounting of plant residues per unit area; 2) field determination of the projective cover by the method of line transects; 3) desk analysis of photographs of the soil surface. Based on the obtained results, models of the linear dependence of NDTI values on the projective cover of the soil surface with plant residues were constructed. The possibility of quantitative accounting of plant residues only on the basis of remote sensing data was also analyzed. The highest coefficient of determination (R2 = 0.97) with the smallest square root of the standard error (RMSE = 7.93) was obtained by modeling based on the analysis of photographs of the soil surface covered with plant residues. Based on the model of the dependence of NDTI values on the projective cover of plant residues obtained as a result of the analysis of photographs based on Sentinel -2 satellite data for the growing season 2020–2021, data were obtained on the dynamics of soil coverage with plant residues (CRC) on the scale of a single field an d different tillage technologies. As an approbation of the approach and an assessment of its use for solving production problems, the dynamics of the projective cover with plant residues was analyzed under different crops and different relief conditions. An analysis of the dynamics of CRC values made it possible to distinguish between different stages of crop cultivation under traditional technology (TT) and no-till (ПП), and also on the scale of an individual field revealed the heterogeneity of the projective soil cover with plant residues associated with the features of the mesorelief.

Improvement of Automotive Sensors by Migrating AUTOSAR End-to-End Communication Protection Library into Hardware

This paper explores new methods to increase the level of safety of data transfer between sensors and electronic control units (ECUs) in automotive communication. A new model of basic sensors to be used in automotive electronics is proposed. This model contains hardware modules that implement the end-to-end communication protection (E2E) mechanism, as defined by the Automotive Open System Architecture (AUTOSAR) standard. By adding this feature inside the sensors, it is possible that, in addition to increasing the safety level, these sensors can be directly connected to the network ECUs via standard communication buses (e.g., Local Interconnect Network (LIN), Controller Area Network (CAN), Flexray, etc.). This paper describes the model, design, and mapping (in a Field Programmable Gate Array device (FPGA)) of the hardware E2E module capable of generating the Cyclic Redundancy Code (CRC) and counter signal for a customized message. This message represents the output of the new sensor E2E module used in a safety communication as requested by the automotive E2E standard. The model is validated also by comparing the data output of the E2E hardware with the data output of the AUTOSAR software E2E library. Finally, future needs and directions are suggested in this area.

Polar Coded Repetition

Constructing efficient low-rate error-correcting codes with low-complexity encoding and decoding has become increasingly important for applications involving ultra-low-power devices such as Internet-of-Things (IoT). To this end, schemes based on concatenating the state-of-the-art codes at moderate rates with repetition codes have emerged as practical solutions deployed in various standards. In this paper, we propose a novel mechanism for concatenating outer polar codes with inner repetition codes which we refer to as polar coded repetition. More specifically, we propose to transmit a slightly modified polar codeword by deviating from Arıkan’s standard <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 \times 2$ </tex-math></inline-formula> Kernel in a certain number of polarization recursions at each repetition block. We show how this modification can improve the asymptotic achievable rate of the standard polar-repetition scheme, while ensuring that the overall encoding and decoding complexity is kept almost the same. The achievable rate is analyzed for the binary erasure channel (BEC) and additive white Gaussian noise (AWGN) channel. Moreover, we show that the finite-length performance of the polar coded repetition scheme under cyclic redundancy check (CRC) aided successive cancellation list (SCL) decoder over AWGN channel is better than the uncoded polar-repetition scheme at the cost of a slight increase in decoding complexity. We also compare the proposed scheme, in terms of performance and complexity, with other low-rate solution based on polar codes in the literature.

Hybrid Non-Binary Repeated Polar Codes

Concatenating the state-of-the-art codes at moderate rates with repetition codes has emerged as a practical solution deployed in various standards for ultra-low-power devices such as in Internet-of-Things (IoT) networks. In this paper, we propose a novel concatenation mechanism for such applications which need to operate at very low signal-to-noise ratio (SNR) regime. In the proposed scheme, the outer code is a hybrid polar code constructed in two stages, one with a binary kernel and another also with a binary kernel but applied over a binary extension field. The inner code is a non-binary multiplicative repetition code. This particular structure inherits low-complexity decoding structures of polar codes while enabling concatenation with an inner non-binary multiplicative repetition scheme. The decoding for the proposed scheme is done using cyclic redundancy check (CRC) aided successive cancellation list (SCL) decoder over additive white Gaussian noise (AWGN) and Rayleigh fading channels. Simulation results demonstrate that the proposed hybrid non-binary repeated polar code provides performance gain compared to a polar-repetition scheme with comparable decoding complexity.

CRC-Aided Adaptive BP Decoding of PAC Codes.

Although long polar codes with successive cancellation decoding can asymptotically achieve channel capacity, the performance of short blocklength polar codes is far from optimal. Recently, Arıkan proposed employing a convolutional pre-transformation before the polarization network, called polarization-adjusted convolutional (PAC) codes. In this paper, we focus on improving the performance of short PAC codes concatenated with a cyclic redundancy check (CRC) outer code, CRC-PAC codes, since error detection capability is essential in practical applications, such as the polar coding scheme for the control channel. We propose an enhanced adaptive belief propagation (ABP) decoding algorithm with the assistance of CRC bits for PAC codes. We also derive joint parity-check matrices of CRC-PAC codes suitable for iterative BP decoding. The proposed CRC-aided ABP (CA-ABP) decoding can effectively improve error performance when partial CRC bits are used in the decoding. Meanwhile, the error detection ability can still be guaranteed by the remaining CRC bits and adaptive decoding parameters. Moreover, compared with the conventional CRC-aided list (CA-List) decoding, our proposed scheme can significantly reduce computational complexity, to achieve a better trade-off between the performance and complexity for short PAC codes.

An Efficient Pro-Active Fault-Tolerance Scheduling of IEEE 802.1Qbv Time-Sensitive Network

Time-sensitive network (TSN) has emerged as one of the enhancement Ethernet technologies of real-time applications for future industrial networks. However, the data of TSN messages may be unexpectedly changed within the transmission duration due to electromagnetic interference. A cyclic redundancy check (CRC) can detect such errors and notify the sender node to retransmit the erroneous message through automatic repeat request (ARQ). The time when the error occurs is uncertain. Consequently, the time when performing the retransmission requests is also random, which results in different transmission sequences and violates the deterministic transmission of TSN. In addition, the returned CRC detection messages also might be at fault during transmission. In order to provide the fault tolerance capability of critical flows in TSN without violating the nature of deterministic transmission, this article proposes a pro-active fault-tolerant TSN scheduling algorithm (PFT-TSN), which not only transmits a certain number of instance copies for critical flows but provides network transmission services for noncritical flows. The challenge is that schedulability and safety of critical flows are tradeoffs in terms of the number of transmissions per instance of critical flows and the schedulability. Moreover, the transmission service of noncritical flows can also affect the schedulability of critical flows. We conduct comprehensive experiments with synthetic networks to show that the proposed method can meet both safety and schedulability requirements for critical flows, and noncritical flows are also allowed to be transmitted by the service degradation.

Numerical analysis of all-optical silicon microring resonator-based cyclic redundancy check encoder

Data are transmitted at a higher rate over long and short distances to fulfill the global requirement using all-optical (AO) technology. The reliability or accuracy of data transmission is also a key factor along with the higher data rate to achieve today’s desire perfectly. The cyclic redundancy check (CRC) code is a powerful, robust, and widely used error detecting code for data communication system and storage devices to find any unintentional changes during transmission. A (7, 4) CRC encoder has been analyzed numerically using AO silicon microring resonator (MRR) at a high-operational speed of 260 Gbps. CRC encoder is designed using MRR-based XOR gates and D flip flops. The proposed CRC encoder circuit is validated through MATLAB simulation. The optimization of essential parameters is accomplished through simulation against various metrics. These parameters could be utilized for practical execution of this design.

Adaptive Belief Propagation Decoding of CRC Concatenated NR LDPC and Polar Codes

In this paper, we propose a modified adaptive belief propagation (ABP) algorithm, which is referred to as the random ABP (R-ABP) algorithm, for decoding short channel codes adopted in the fifth generation (5G) New Radio (NR) wireless systems. Based on the cyclic redundancy check (CRC) concatenation structure of 5G channel codes, we can take partial or even all CRC bits into iterative R-ABP decoding to improve the error correction performance, while the error detection capability can still be guaranteed by the remaining CRC bits and a proposed threshold-based acceptance criterion. We call this improved R-ABP decoding the threshold-and-CRC-aided R-ABP (TCA-R-ABP) decoding. The simulation results show that our proposed TCA-R-ABP algorithm outperforms the state-of-the-art decoding algorithms for many 5G low-density parity-check (LDPC) and polar codes. Moreover, the proposed TCA-R-ABP algorithm leads to a unified decoder for LDPC and polar codes, which has the potential to be a lower-complexity decoder over the combination of the belief propagation (BP) and CRC-aided successive cancellation list (CA-SCL) decoders.

Perancangan dan Implementasi Encoder dan Decoder CRC-8 untuk Pendeteksian Error pada Transmisi Data antar Perangkat IoT

Cyclic Redundancy Check (CRC) is a widely used error detection code in digital communication systems to detect errors in data transmitted between transmitter and receiver. With the development of Internet-of-Things (IoT) technology, where many devices communicate wirelessly, the application of error detection codes such as CRC is essential to obtain reliable communication. The computation of CRC can be implemented in hardware using a linear feedback shift register (LFSR) or in software with shift and bitwise exclusive OR (XOR) operations for polynomial division. Due to the frequent use of CRC in wireless communication for IoT, research for the design and implementation of CRC continues to this day. This study aims to design and implement the encoder and decoder of CRC-8 with generator polynomial 0x07 on IoT devices. Two algorithms for computing the CRC, namely bitwise computation using LFSR and another one using lookup tables, are implemented on the Arduino Uno R3 board. Two Arduino boards connected in serial were used to verify the encoder and decoder implementation in the data transmission and error detection process. The experiment results showed that the encoder could correctly calculate the CRC value from the input data. Furthermore, the computation using lookup tables takes about four times faster than the bitwise method but requires more memory. In contrast, the bitwise computation method requires less memory but slower computation time. When testing using input data of 128 characters, the bitwise-based encoder requires a computation time of 2.37 milliseconds, while the lookup table-based encoder utilizing a lookup table requires a computation time of 0.5 milliseconds. In the error detection test, the results demonstrated that the receiver could detect errors in the transmitted data with a percentage of 100%.

Study of Different Types of Error Detection and Correction Code in Wireless Communication

The integrity of received data is a critical consideration in the design of digital communications and storage systems. The technique involved in attaining data reliability while transmission over a wireless channel is to use Channel Coding. These coding methods involve the use of Error Control Codes and there are two basic ways of controlling errors. They are Automatic Repeat Request and Forward Error Correction. This thesis concentrates on Forward error correction that deals with error detection and error correction. There are two types of error control codes: Block Codes and Convolutional Codes. The extent to which the errors are detected is a measure of the success of the code. The main trade-off in the error correction/detection technique lies in the key parameters involved in evaluating a coding system. Various block codes are analyzed using the performance metrics, namely, Improvement ratio and Error Resilience. It is observed that Cyclic Redundancy Check (CRC) codes showed better performance, and hence, they are chosen for further study.

Hardware Designs of Cyclic Redundancy Check Code with Calculation Time Trade-Off Strategy

This paper will discuss the design of cyclic redundancy check code (CRC), a most popular error detecting scheme in intelligent communication. At first, the concepts of CRC are given in detail with mathematical model and software simulation in python scripts. And mainly, with calculation time trade-off strategy, we provide the CRC hardware design with three architecture models serial, parallel, hybrid serial and parallel. Keywords: Error Detection Scheme; Cyclic Redundancy Check; Python; Verilog HDL; Digital System Design

CRC-Aided List Decoding of Convolutional Codes in the Short Blocklength Regime

We consider the concatenation of a convolutional code (CC) with an optimized cyclic redundancy check (CRC) code as a promising paradigm for good short blocklength codes. The resulting CRC-aided convolutional code naturally permits the use of serial list Viterbi decoding (SLVD) to achieve maximum-likelihood decoding. The convolutional encoder of interest is of rate-$1/\omega$ and the convolutional code is either zero-terminated (ZT) or tail-biting (TB). The resulting CRC-aided convolutional code is called a CRC-ZTCC or a CRC-TBCC. To design a good CRC-aided convolutional code, we propose the distance-spectrum optimal (DSO) CRC polynomial. A DSO CRC search algorithm for the TBCC is provided. Our analysis reveals that the complexity of SLVD is governed by the expected list rank which converges to $1$ at high SNR. This allows a good performance to be achieved with a small increase in complexity. In this paper, we focus on transmitting $64$ information bits with a rate-$1/2$ convolutional encoder. For a target error probability $10^{-4}$, simulations show that the best CRC-ZTCC approaches the random-coding union (RCU) bound within $0.4$ dB. Several CRC-TBCCs outperform the RCU bound at moderate SNR values.

A Soft-Input Soft-Output Polar Decoding Algorithm for Turbo-Detection in MIMO-Aided 5G New Radio

Soft-Input Soft-Output (SISO) polar decoding algorithms, such as Belief Propagation (BP) and Soft Cancellation (SCAN) polar decoding, offer iteration capability for facilitating turbo-style detection. However, at lower Signal-to-Noise Ratios (SNRs), the performance of the BP and SCAN decoders is about 1.5 dB and 0.5 dB worse than that of the state-of-the-art hard-decision Successive Cancellation List (SCL) decoding algorithm, respectively, despite iteratively exchanging information with a Multiple Input Multiple Output (MIMO) detector. Motivated by this gap, we conceive a novel G-SCAN polar decoder, which generates both soft-decision and hard-decision outputs. This is achieved by intrinsically amalgamating a list decoder with a novel SISO decoder. These soft-decision outputs may be used for turbo-detection, but they also support the hard-decision outputs of the SCL algorithm for achieving superior block error rate (BLER) performance. As a result of these benefits, the proposed G-SCAN algorithm using a list size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L = 2$</tex-math></inline-formula> offers around 1 dB BLER gain compared to the conventional hard-decision SCL decoder relying on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$L = 32$</tex-math></inline-formula> . Furthermore, we have carried out its Extrinsic Information Transfer (EXIT) chart analysis, and characterized the performance vs. the complexity of the proposed G-SCAN algorithm, and compared it to various soft- and hard-decision output benchmarks for a wide variety of different rate-matching modes and block lengths. Furthermore, in order to reduce the complexity of the proposed algorithm, a novel Cyclic Redundancy Check (CRC)-aided G-SCAN algorithm is also proposed, which facilitates early termination and improves the BLER performance.

Penerapan Metode CRC32 dalam Mendeteksi Orisinalitas File Video

One of the courses in higher education, especially in the field of computers, is cryptography. The rapid development of technology today proves that it is easy to commit crimes using computer science in the video field. In addition, from time to time more and more free video editing software and easier to use. However, the development of this technology is often misused by cases of scattered videos that cannot be trusted by the public. Video file forgery is an act of modifying documents, products, images or videos among other media. This video, which is very easy to edit and fake, has made many irresponsible people destroy the authenticity of the video and spread the video to social media so that the information or message in the video can change its authenticity. Computer-based learning is one way to improve the quality of learning. Various methods that can be applied in computer-based learning, one of which is CRC32 (Cyclic Redundancy Check) can be used to ensure the integrity of the data to be transmitted or stored. CRC works in a simple way, namely by using a mathematical calculation of a number called a checksum, which is made based on the total bits to be transmitted or to be stored. CRC is designed in such a way as to ensure data integrity against random degradation due to noise or other sources (media corruption etc.). So that later the learning application that will be made can help students in the process of answering about material concerning the authenticity of a video file more easily and can be understood using the CRC32 method. In addition, it is hoped that the learning application which will be made more interactive is able to attract students' interest to be more curious

On the Improper Use of CRC for Cryptographic Purposes in RFID Mutual Authentication Protocols

Mutual authentication is essential to guarantee the confidentiality, integrity, and availability of an RFID system. One area of interest is the design of lightweight mutual authentication protocols that meet the limited computational and energy resources of the tags. These protocols use simple operations such as permutation and cyclic redundancy code for cryptographic purposes. However, these functions are cryptographically weak and are easily broken. In this work, we present a case against the use of these functions for cryptographic purposes, due to their simplicity and linear properties, by analyzing the LPCP protocol. We evaluate the claims of the LPCP resistance to de-synchronization and full disclosure attacks and show that the protocol is weak and can be easily broken by eavesdropping on a few mutual authentication sessions. This weakness stems from the functions themselves as well as the improper use of inputs to these functions. We further offer suggestions that would help in designing more secure protocols.

Analysis and Design of CRC-32 IEEE 802.3 Generator for 8 Bit Data Using VHDL

In the communication system to achieve better quality data transmission required a method that can detect errors and correct errors. Cyclic Redundancy Check (CRC) is one of the methods used to perform data transmission on data link layer that can detect errors. CRC-32 is used to error-checking on Ethernet or implemented to IEEE 802.3. CRC generator in this research use CRC-32 IEEE 802.3 with 8 bit data width. This research can be implemented in the field of Electrical Engineering, especially in the telecommunications section, namely Ethernet which functions for transfer files and data via a computer network. CRC here has a role to prevent data changes caused by noise during the transmission process. The methods used in this design is modulo-2 division parallel circuit. This design is expected to use a simple schematic circuit, less noise and less resources. Testing is done by matching result of simulation using Xilinx ISE Simulator with implementation on Spartan 3E XC3S500E device with result of count . This research requires a resource of 223 4-input LUTs, 114 Occupied slice, 72 IOB flip flops, 114 bonded IOBs and 1 BUFGMUXs, where this research obtained resources is fewer than with previous research

Partial Order-Based Decoding of Rate-1 Nodes in Fast Simplified Successive-Cancellation List Decoders for Polar Codes

Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List (SCL) decoding supported by a Cyclic Redundancy Check (CRC) shows the best error-correction performance at the cost of a high decoding complexity. The decoding of Rate-1 nodes belongs to the most complex tasks in SCL decoding. In this paper, we present a new algorithm that largely reduces the number of considered candidates in a Rate-1 node and generate all required candidates in parallel. For this purpose, we use a partial order of the candidate paths to prove that only a specified number of candidates needs to be considered. Further complexity reductions are achieved by an extended threshold-based path exclusion scheme at the cost of negligible error-correction performance loss. We present detailed Application-Specific Integrated Circuit (ASIC) implementation data on a 28 nm Fully Depleted Silicon on Insulator (FD-SOI) Complementary Metal-Oxide-Semiconductor (CMOS) technology for decoders with code length 128. We show that the new decoders outperform state-of-the-art reference decoders. For list size 8, improvements of up to 158.8% and 62.5% in area and energy efficiency are observed, respectively.

Efficient Reservation-based Fault-Tolerant Scheduling for IEEE 802.1Qbv Time-Sensitive Networking

Time-Sensitive Networking (TSN) is one of the enhanced Ethernet technologies for the real-time application of industrial networks in the future. However, unexpected data errors caused by transient influence like electromagnetic interference may be occurred during the data transmission. One common way to tolerate such failures is to directly transmit multiple instance copies, such as IEEE 802.1 CB. However, wasting limited network resources is one of the drawbacks, since not all message copies could be received incorrectly. Cyclic Redundancy Check (CRC) can detect such errors when data is received, then the detection result is notified to the sending node. Despite that the re-transmission is performed only if the returned detection result is negative or time-out, the occurrence of errors are uncertain. Consequently, the time when responding to the re-transmission requests is also random, which results in different transmission sequences and violates the deterministic transmission service of TSN. Furthermore, CRC detection results messages also might be fault during transmission. To tackle the above drawbacks, we propose a novel offline reservation-based fault-tolerance scheduling algorithm for IEEE 802.1 Qbv TSN. Firstly, the Dijkstra algorithm is used to generate the routing for each flow. Then, the resource allocation is generated by Satisfiability Modulo Theories according to TSN constraints formulated to guarantee the deterministic transmission for Time-Trigger (TT) flows, CRC-related flows, and the reserved re-transmissions of TT flows. Finally, the queues are also open for non-TT flows in the time slice reserved for re-transmissions of TT flows to enhance the throughput of non-TT flows. Through extensive simulations, we demonstrate the effectiveness of the proposed approach in terms of acceptance ratio, execution time and the wasted resources.

Enhancement of safety communication model

Abstract A fundamental measure of safety communication is the residual error probability, i. e., the probability of undetected errors. For the detection of data errors, typically a Cyclic Redundancy Check (CRC) is applied, and the resulting residual error probability is determined based on the Binary Symmetric Channel (BSC) model. The use of this model had been questioned since several error types cannot be sufficiently described. Especially the increasing introduction of security algorithms into underlying communication layers requires a more adequate channel model. This paper introduces an enhanced model that extends the list of considered data error types by combining the BSC model with a Uniformly Distributed Segments (UDS) model. Although models beyond BSC are applied, the hitherto method of the calculation of the residual error probability can be maintained.