Cyclic Redundancy Research Articles

Design and proof of concept of a double-panel TOF-PET system

ObjectivePositron Emission Tomography (PET) is a well-known imaging technology for the diagnosis, treatment, and monitoring of several diseases. Most PET scanners use a Ring-Shaped Detector Configuration (RSDC), which helps obtain homogeneous image quality but are restricted to an invariable Field-of-View (FOV), scarce spatial resolution, and low sensitivity. Alternatively, few PET systems use Open Detector Configurations (ODC) to permit an accessible FOV adaptable to different target sizes, thus optimizing sensitivity. Yet, to compensate the lack of angular coverage in ODC-PET, developing a detector with high-timing performance is mandatory to enable Time-of-Flight (TOF) techniques during reconstruction.The main goal of this work is to provide a proof of concept PET scanner appropriate for constructing the new generation of ODC-PET suitable for biopsy guidance and clinical intervention during acquisition. The designed detector has to be compact and robust, and its requirements in terms of performance are spatial and time resolutions < 2 mm and < 200 ps, respectively.MethodsThe present work includes a simulation study of an ODC-PET based on 2-panels with variable distance. The image quality (IQ) and Derenzo phantoms have been simulated and evaluated. The phantom simulations have also been performed using a ring-shaped PET for comparison purposes of the ODC approach with conventional systems. Then, an experimental evaluation of a prototype detector that has been designed following the simulation results is presented. This study focused on tuning the ASIC parameters and evaluating the scintillator surface treatment (ESR and TiO2), and configuration that yields the best Coincidence Time Resolution (CTR). Moreover, the scalability of the prototype to a module of 64 × 64mm2 and its preliminary evaluation regarding pixel identification are provided.ResultsThe simulation results reported sensitivity (%) values at the center of the FOV of 1.96, 1.63, and 1.18 for panel distances of 200, 250, and 300 mm, respectively. The IQ reconstructed image reported good uniformity (87%) and optimal CRC values, and the Derenzo phantom reconstruction suggests a system resolution of 1.6–2 mm.The experimental results demonstrate that using TiO2 coating yielded better detector performance than ESR. Acquired data was filtered by applying an energy window of ± 30% at the photopeak level. After filtering, best CTR of 230 ± 2 ps was achieved for an 8 × 8 LYSO pixel block with 2 × 2 × 12mm3 each. The detector performance remained constant after scaling-up the prototype to a module of 64 ×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document} 64mm2, and the flood map demonstrates the module’s capabilities to distinguish the small pixels; thus, a spatial resolution < 2 mm (pixel size) is achieved.ConclusionsThe simulated results of this biplanar scanner show high performance in terms of image quality and sensitivity. These results are comparable to state-of-the-art PET technology and, demonstrate that including TOF information minimizes the image artifacts due to the lack of angular projections. The experimental results concluded that using TiO2 coating provide the best performance. The results suggest that this scanner may be suitable for organ study, breast, prostate, or cardiac applications, with good uniformity and CRC.

Reliability of Arduino Serial Communication Systems: A Case Study on the Application of Cyclic Redundancy Check (CRC)

In embedded systems, serial communication plays a crucial role in data transfer, particularly in Arduino-based projects. However, factors such as electromagnetic interference, noise, and signal degradation can compromise data integrity, leading to significant errors. Effective error detection systems are essential to ensure reliable data exchange. The Cyclic Redundancy Check (CRC) is one such method known for its ability to detect errors. Despite its potential, the practical application and impact of CRC on Arduino communication systems have not been extensively explored. This study implements CRC within Arduino serial communication by designing and developing software that integrates CRC for real-time error detection. The study rigorously tests this implementation in various scenarios to evaluate its performance, comparing data integrity with and without CRC. The results show that incorporating CRC significantly improves the reliability of data transmission in Arduino applications, enhancing error detection accuracy. This improvement strengthens existing systems and provides a solid foundation for developing more complex communication frameworks. The research advances reliable communication systems in embedded technologies. By demonstrating CRC's effectiveness in enhancing data integrity, the study offers valuable insights for developers and researchers seeking to improve serial communication across different applications.

Enhancing Data Security through Hybrid Error Detection: Combining Cyclic Redundancy Check (CRC) and Checksum Techniques

Enhancing Data Security through Hybrid Error Detection: Combining Cyclic Redundancy Check (CRC) and Checksum Techniques

An energy efficient authentication scheme for cluster-based wireless IoT sensor networks

Wireless Internet of Things (IoT) sensor networks (WITSN) play a pivotal role in modern society, facilitating a myriad of applications ranging from smart homes to industrial automation. Therefore, safeguarding these networks against security threats is paramount to ensure the integrity, confidentiality, and availability of data transmitted within them. However, WITSNs face escalating security threats due to their diverse structures and platforms. Existing literature has identified these vulnerabilities but lacks comprehensive solutions to address them effectively. To bridge this gap, this paper proposes a novel security approach termed Randomized Bi-Phase Authentication Scheme (RBAS), which integrates digital watermarking techniques to fortify both external and internal network security. RBAS not only tackles data availability, confidentiality, and authenticity challenges prevalent in WITSNs but also strives to maintain a delicate equilibrium between robust security measures and energy efficiency. Key contributions of this work include the meticulous examination and validation of the integration of cyclic redundancy check (CRC) codes in IoT sensor network authentication, demonstrating their efficacy in error detection through simulations. Furthermore, RBAS employs advanced hashing, cryptography, and dynamic verification codes to ensure strong error detection and data authenticity, leveraging robust CRC codes and randomization to thwart potential attacks. The scheme's complexity acts as a deterrent against manipulation, while its cluster awareness enhances adaptability, and cryptographic principles bolster overall security. Extensive performance evaluation using the Network Simulator-2 (NS2) reveals significant benefits of RBAS, including an 8 % reduction in power consumption and a 7 % increase in network longevity. Notably, RBAS surpasses existing solutions with a 14 % reduction in dropping ratio and an 8 % decrease in latency. The success of RBAS stems from its innovative utilization of lightweight watermarking techniques and cluster-based routing, enabling proactive identification of data tampering and thereby enhancing the network's overall security posture. This pioneering work not only advances the state of the art in WITSN security but also holds profound implications for the practical deployment of secure and efficient IoT sensor networks in real-world scenarios.

Chaotic Phase Modulation Direct-Sequence Spread Spectrum-Assisted Adaptive Serial Cancellation List Decoding Method for Underwater Acoustic Communication

Addressing the challenges of high decoding latency, reduced spectral efficiency, and substantial storage requirements in a Cyclic Redundancy Check (CRC)Aided Successive Cancellation List (CA-SCL) polar decoder, this paper proposes a chaotic phase modulation direct-sequence spread spectrum (CPMDSSS)-assisted adaptive serial cancellation list decoding method for underwater acoustic communication. The method involves segmenting the information bits to be transmitted, computing CRC for each segment, and mapping all CRCs to a CPMDSSS, which is then modulated onto the pilot subcarriers of underwater acoustic orthogonal frequency-division multiplexing (OFDM) to increase spectral efficiency. At the receiving end, CRCs are obtained by demodulating the CPMDSSS to verify the segmented information and adaptively select the number of decoding paths. The theoretical analysis and simulation results demonstrate that compared to CA-SCL, the proposed method effectively reduces the required storage units and improves spectral efficiency, with an average reduction of approximately 80% in the decoding paths. Sea trials further indicate that the proposed method reduces the average decoding paths by approximately 71% and decreases the average decoding delay by approximately 64% compared to CA-SCL.

Leveraging CRC Error Detection for Enhanced Error Correction in Digital Communication Systems

In this study, CRC error detection techniques will be used to not only identify but fix single-bit errors in digital communication systems. In the past, CRC codes have been employed mainly for their ability to detect errors efficiently. However, this paper suggests a new way that will make it possible to modify CRC functions and thus correct the identified errors. It is intended that by using an optimized look-up table in Verilog hardware description language with an advanced Xilinx 14.7 toolchain, this research can increase the dependability and effectiveness of error correction mechanisms found in digital systems. The study presents how to create a detailed hardware description, optimize lookup tables for minimal resource usage and increased error correction capability; then synthesizes design with Xilinx 14.7.The conclusion makes a practical contribution towards identification and removal of single-bit errors which indicates a turning point in the use of Cyclic Redundancy Check (CRC) technology from being just about error detection to full scale error correction. This enhancement has the potential to greatly increase the durability and reliability of data transmission and storage systems, especially in critical applications requiring utmost data integrity. Keywords: Cyclic Redundancy Check (CRC), Error detection, Single-bit errors, Optimized lookup table, Xilinx 14.7 toolchain.

A tactical data link model based on CCSK-FMSK

In collaborative combat operations, the challenges brought by the communication adversities of tactical data links are becoming increasingly prominent. Ensuring the reliable connection of tactical data links has always been a key issue, especially considering the increasing impact of external interference on the signal at the receiving end of the system, which in turn affects the bit error rate (BER) of the tactical data link system. To address this challenge, this paper proposes a tactical data link anti-interference scheme based on cyclic code shift keying (CCSK) spread spectrum and minimum shift keying (MSK) modulation fusion frequency hopping technology, named CCSK-FMSK, and introduces turbo code and cyclic redundancy check (CRC) coding to construct a tactical data link model based on CCSK-FMSK. Specifically, CCSK-FMSK disperses interference power by expanding the signal spectrum, enhancing the anti-interference ability of tactical data links. CRC coding and Turbo coding achieve error detection and correction by introducing supervised symbols. In addition, this paper proposes a soft despreading and a soft demodulation algorithm corresponding to CCSK spread spectrum and MSK modulation to achieve cascade with Turbo decoder and improve the error rate performance and robustness of the model. Compared with existing models, the tactical data link based on CCSK-FMSK has better BER performance.

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0

Dynamic Voltage and Frequency Scaling as a Method for Reducing Energy Consumption in Ultra-Low-Power Embedded Systems

Dynamic voltage and frequency scaling (DVFS) is a technique used to optimize energy consumption in ultra-low-power embedded systems. To ensure sufficient computational capacity, the system must scale up its performance settings. The objective is to conserve energy in times of reduced computational demand and/or when battery power is used. Fast Fourier Transform (FFT), Cyclic Redundancy Check 32 (CRC32), Secure Hash Algorithm 256 (SHA256), and Message-Digest Algorithm 5 (MD5) are focused functions that demand computational power to achieve energy-efficient performance. Selected operations are analyzed from the energy consumption perspective. In this manner, the energy required to perform a specific function is observed, thereby mitigating the influence of the instruction set or system architecture. For stable operating voltage scaling, an exponential model for voltage calculation is presented. Statistical significance tests are conducted to validate and support the findings. Results show that the proposed optimization technique reduces energy consumption for ultra-low-power applications from 27.74% to up to 47.74%.

An Experimental Performance Assessment of Galileo OSNMA.

We present Galileo Open Service Navigation Message Authentication (OSNMA) observed operational information and key performance indicators (KPIs) from the analysis of a ten-day-long dataset collected in static open-sky conditions in southern Finland and using our in-house-developed OSNMA implementation. In particular, we present a timeline with authentication-related events, such as authentication status and type, dropped navigation pages, and failed cyclic redundancy checks. We also report other KPIs, such as the number of simultaneously authenticated satellites over time, time to first authenticated fix, and percentage of authenticated fixes, and we evaluate the accuracy of the authenticated position solution. We also study how satellite visibility affects these figures. Finally, we analyze situations where it was not possible to reach an authenticated fix, and offer our findings on the observed patterns.

Design of Intelligent City Communication Network Based on Internet of Things

Abstract In response to the advancements in Internet of Things (IoT) technology and the growing demands for data transmission, there is a crucial need for further integration of communication network technology with IoT to enhance efficiency. This paper presents the design of a multi-node communication network model utilizing the Orthogonal Frequency-Division Multiplexing (OFDM) algorithm. In the realm of physical layer parameter design, uplink, and downlink carriers are allocated based on OFDM symbols, employing the Zadoff-Chu (ZC) sequence as the pilot frequency sequence. Additionally, the Cyclic Redundancy Check (CRC) error-checking code is implemented to ensure the accuracy of network transmissions. The model proposed in this study is applied to the operational dynamics of traffic systems within a smart city, focusing on the security and operational efficiency of the traffic communication network. Empirical testing and analysis demonstrate that the communication network, as designed, is susceptible to malware attacks by 25.68%, representing the least vulnerability among the three algorithms assessed. Moreover, in examining the bus trip time distribution with the implementation of this model, the average running time is predominantly around 11.76 minutes, which is a reduction of 0.74 minutes compared to previous configurations, thereby indicating an improvement in operational efficiency.

High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

Near-infrared signature of hydrothermal opal: a case study of Icelandic silica sinters

Abstract. Silica minerals constitute a main target to assess the origin of life or the possibility of its emergence. On Earth, ancient hydrothermal silica deposits have preserved the oldest forms of life. Beyond Earth, such silica-rich hydrothermal systems have been observed on Mars by orbital near-infrared (NIR) remote sensing and in situ rover exploration. This work investigates the variations of texture and NIR properties of opal with temperature, within a single geological context of hot springs. Silica sinters have been sampled in Icelandic hot-spring fields, in the Reykholt region, and at the Hveravellir site, with water temperature ranging from 14 to 101 ∘C. Variations in the NIR spectral features (concavity ratio criteria, CRC) vary with fluid temperature, lithofacies, and microtexture. Only high-temperature samples display high CRC values (CRC5200&gt;0.85), but low CRC values (CRC5200 &lt; 0.75) are measured for any temperature. Hence, temperature is not the only parameter controlling spectral properties of opal. Several other parameters such as the hydrodynamic context, the microbial activity, silica micro-textures, and porosity may also affect silica precipitation, the incorporation and speciation of water in it, and thus its NIR signature. The observations suggest a limitation in the use of NIR spectral features for the interpretation of the geological context of fossil opal on Earth or Mars: only opal with high CRC values can be inferred as being formed by hydrothermal activity. Low CRC values can be attributed to either low-temperature hydrothermal activity (&lt; 50–60 ∘C) or to continental weathering.

Cyclic redundancy check-aided successive cancellation-based polar decoders

&lt;span&gt;Research on channel coding for network transmission using polar codes has produced excellent results. By removing error redundancy from the decoding process, cyclic redundancy check (CRC) is frequently used by researchers to increase a system’s performance. In prior research, the application of decoder algorithms for polar codes was examined but not thoroughly compared. For the general capabilities of the previously proposed algorithms to be ascertained, it is crucial to analyze the employment of polar decoders especially successive cancellation (SC)-based polar decoders and the use of CRC in additive white gaussian noise (AWGN). Hence, this paper analyzes the performance of CRC with SC-based polar decoders in AWGN. In the simulation setup, (256,128) polar codes and CRCs with three-bit sizes (6, 8 and 11) were utilized. SC-based polar decoders, such as SC, soft-output cancellation, SC list (SCL) and simplified SC, were applied at the decoder part. The outcomes show that CRC-aided SC-based polar decoders reduced redundancy error. Among all the decoders, the SCL decoder with 11-bits CRC performed well when the normalized signal-to-noise ratio was high. Based on the analysis, removing errors at the highest level is possible using a suitable CRC size for SC-based polar decoders.&lt;/span&gt;

Design and implementation of ternary cyclic redundancy code based on ternary optical computer

In order to meet the multiple requirements of error checking in ternary optical computer (TOC), cyclic redundancy check (CRC) is introduced into ternary optical computers and the research on ternary cyclic redundancy check (T-CRC) is carried out. Combining the characteristics of MSD (Modefied Signed-Digit) digital system and the concept of cyclic redundancy check, this paper studies T-CRC based on ternary optical computer, and proposes the operation rules of modular 3 division and two basic operations to assist in calculating the check bits of T-CRC. In order to avoid the complicated one-step iterative modular 3 division and realize the fast computation of check bits of T-CRC, a two-step parallel computation scheme of T-CRC is proposed. In the parallel computing scheme, the original single step iterative division operation is replaced by table look-up and special parity check code splicing, and the optical path structure of auxiliary operation is designed, which greatly reduces the computational difficulty of check bit in T-CRC. Finally, the parallel algorithm experiment is carried out on the ternary optical computer platform, and the experimental results are completely consistent with the theoretical calculation results, proving that it is completely feasible.

Design of SENT signal acquisition system based on LabVIEW

With the emergence of single-edge nibble transmission (SENT) signals in the field of automotive sensors, equipping major vehicle manufacturing companies with a set of well-functioning SENT signal acquisition systems has become an essential requirement. At present, we have designed a SENT signal acquisition system to satisfy this requirement and provide a practical option for companies. The acquisition system is based on the SENT J2716 communication protocol. A master control circuit with an STM8AF6213 microcontroller as the core is used to capture the sensor output signal and apply C language programming to realize the decoding of the signal. Finally, the data are processed, extracted, and preserved by the LabVIEW program to achieve the purpose of data visualization. In order to ensure the accuracy of the data, a double Cyclic Redundancy Check (CRC) checksum mode is incorporated into the system. After completion, the system was applied to several sets of SENT signal acquisition and testing experiments, and the experimental results all showed that the system operated normally and could meet the requirements of companies.

Pre-Configured Error Pattern Ordered Statistics Decoding for CRC-Polar Codes.

In this paper, we propose a pre-configured error pattern ordered statistics decoding (PEPOSD) algorithm and discuss its application to short cyclic redundancy check (CRC)-polar codes. Unlike the traditional OSD that changes the most reliable independent symbols, we regard the decoding process as testing the error patterns, like guessing random additive noise decoding (GRAND). Also, the pre-configurator referred from ordered reliability bits (ORB) GRAND can better control the range and testing order of EPs. An offline-online structure can accelerate the decoding process. Additionally, we also introduce two orders to optimize the search order for testing EPs. Compared with CRC-aided OSD and list decoding, PEPOSD can achieve a better trade-off between accuracy and complexity.

Performance of polar codes with low complexity cyclic redundancy check aided bit‐flipping for successive cancellation list decoding over power line channels

SummaryPower lines have complex transmission characteristics and noise interference when used as information transmission channel, thus limiting their data‐carrying rate and reliability. Impulsive noise is the most dominant factor degrading the performance of communication systems over power lines. To combat the impulsive noise, polar codes are introduced into the orthogonal frequency division multiplexing (OFDM)‐based power line communication (PLC) system. Because the successive cancelation list bit‐flip (SCLF) decoding algorithm of polar codes has high decoding complexity, a low complexity segmented cyclic redundancy check (CRC)‐aided SCLF decoding is proposed to improve the decoding performance. The decoding process can be terminated early with segmented CRC, which can reduce the bit‐flip decoding complexity significantly with short and medium block lengths. Experimental results demonstrate that for various configurations, the proposed decoder outperforms the traditional CRC‐aided SCL decoder in terms of decoding performance and complexity, and the suggested polar codes‐based OFDM‐based PLC system can reduce the bit error rate of the system in the presence of impulsive noise.

Error‐rate analysis of polar code designs using genetic algorithm for additive white Gaussian noise channel

SummaryA novel scheme for designing polar codes with specific decoding schemes in the additive white Gaussian noise channel is presented in this paper. The code construction strategy is built on the genetic algorithm (GA) where successive evolution of populations (or group of information sets) leads toward fittest candidate to attain finest error‐rates. In this work, it is shown that better error‐rates can be attained by both successive cancelation list decoding using GA with no cyclic redundancy check (CRC) and belief propagation decoding using GA with no CRC and no list, compared to existing polar decoding schemes. Our proposed polar code design scheme using GA has the ability to attain a target block error rates with the least possible SNR and using no additional CRC by exploiting least belief propagation iterations or lesser successive cancelation list list size with no self‐alterations in the decoding algorithm.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.