Cyclic Redundancy Check Implementations Research Articles

Perancangan dan Implementasi Encoder dan Decoder CRC-8 untuk Pendeteksian Error pada Transmisi Data antar Perangkat IoT

Cyclic Redundancy Check (CRC) is a widely used error detection code in digital communication systems to detect errors in data transmitted between transmitter and receiver. With the development of Internet-of-Things (IoT) technology, where many devices communicate wirelessly, the application of error detection codes such as CRC is essential to obtain reliable communication. The computation of CRC can be implemented in hardware using a linear feedback shift register (LFSR) or in software with shift and bitwise exclusive OR (XOR) operations for polynomial division. Due to the frequent use of CRC in wireless communication for IoT, research for the design and implementation of CRC continues to this day. This study aims to design and implement the encoder and decoder of CRC-8 with generator polynomial 0x07 on IoT devices. Two algorithms for computing the CRC, namely bitwise computation using LFSR and another one using lookup tables, are implemented on the Arduino Uno R3 board. Two Arduino boards connected in serial were used to verify the encoder and decoder implementation in the data transmission and error detection process. The experiment results showed that the encoder could correctly calculate the CRC value from the input data. Furthermore, the computation using lookup tables takes about four times faster than the bitwise method but requires more memory. In contrast, the bitwise computation method requires less memory but slower computation time. When testing using input data of 128 characters, the bitwise-based encoder requires a computation time of 2.37 milliseconds, while the lookup table-based encoder utilizing a lookup table requires a computation time of 0.5 milliseconds. In the error detection test, the results demonstrated that the receiver could detect errors in the transmitted data with a percentage of 100%.

Low-Cost and Programmable CRC Implementation Based on FPGA

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions encounter the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with small and constant resource utilization. The experimental results show that the resource utilization of the proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than that of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has lower resource utilization, by 81.7%-85.9% and 2.9%-20.8%, than two state-of-the-art architectures. Furthermore, throughput and programmability are guaranteed. The source code has been made available on -1.5mm]Please cite reference [1] in the text of the paper. It was removed from the abstract as having references in an abstract is contrary to IEEE journal style. GitHub.

Data File Standard for Flow Cytometry, Version FCS 3.2.

FCS 3.2 is a revision of the flow cytometry data standard based on a decade of suggested improvements from the community as well as industry needs to capture instrument conditions and measurement features more precisely. The unchanged goal of the standard is to provide a uniform file format that allows files created by one type of acquisition hardware and software to be analyzed by any other type. The standard retains the overall FCS file structure and most features of previous versions, but also contains a few changes that were required to support new types of data and use cases efficiently. These changes are incompatible with existing FCS file readers. Notably, FCS 3.2 supports mixed data types to, for example, allow FCS measurements that are intrinsically integers (e.g., indices or class assignments) or measurements that are commonly captured as integers (e.g., time ticks) to be more represented as integer values, while capturing other measurements as floating-point values in the same FCS data set. In addition, keywords explicitly specifying dyes, detectors, and analytes were added to avoid having to extract those heuristically and unreliably from measurement names. Types of measurements were formalized, several keywords added, others removed, or deprecated, and various aspects of the specification were clarified. A reference implementation of the cyclic redundancy check (CRC) calculation is provided in two programming languages since a correct CRC implementation was problematic for many vendors. © 2020 International Society for Advancement of Cytometry.

Design and Implementation of Cyclic Redundancy Check with Variable Computing Width Based on Formula Recursive Algorithm

Cyclic Redundancy Check (CRC) is used in cascade with channel coding to improve the convergence of the decoding. In the new generation of wireless communication systems, such as 5G, both code length and code rate are diverse. To improve the decoding efficiency of cascaded systems, a CRC parallel algorithm with variable computing width is proposed in this paper. Based on the existing fixed bit-width parallel algorithm, this algorithm combines the parallel calculation of feedback data and input data in the formula recursive method, realizing a highly parallel CRC check architecture with variable bit-width CRC calculation. Compared with the existing parallel algorithms, the merged algorithm saves the overhead of circuit resources. When the bit-width is fixed, the resource saving effect is obvious, and at the same time, the feedback delay is also optimized by nearly 50%. When the bit-width is variable, the use of resources is also optimized accordingly.

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

Cyclic Redundancy Check (CRC) is often employed in data storage and communications to detect errors. The 3GPP-LTE wireless communication standard uses a 24-bit CRC with every turbo coded frame, thus, the CRC can be exploited to detect residual errors and to enable early stopping of iterations as well. The current state of the art lacks specific CRC implementations for this standard, and most current solutions adopt a fixed degree of parallelism, unsuitable for many turbo decoder architectures. This work proposes a variable parallelism circuit targeting the 3GPP-LTE/LTE-Advanced 24-bit CRC, that can adapt to input data of different sizes. Low complexity is achieved through careful functional sharing among the various parallelisms: comparison with the state of the art shows comparable or superior speed and extremely low complexity.

VLSI Implementation of Parallel CRC Using Pipelining, Unfolding and Retiming

Abstract : Error detection is important whenever there is a non-zero chance of data getting corrupted. A Cyclic Redundancy Check (CRC) is the remainder, or residue, of binary division of a potentially long message, by a CRC polynomial. This technique is ubiquitously employed in communication and storage applications due to its effectiveness at detecting errors and malicious tampering. The hardware implementation of a bit-wise CRC is a simple linear feedback shift register. Such a circuit is very simple and can run at very high clock speeds, but it requires the stream to be bit-serial. This means that ‘n’ clock cycles will be required to calculate the CRC values for an n-bit data stream. This latency is intolerable in many high speed data networking applications where data frames need to be processed at high speed and hence implementation of CRC generation and checking on a parallel stream of data becomes desirable. This paper presents implementation of parallel Cyclic Redundancy Check (CRC) based upon DSP algorithms of pipelining, retiming and unfolding. The architectures are first pipelined to reduce the iteration bound by using novel look-ahead techniques and then unfolded and retimed to design high speed parallel circuits. This paper presents the comparison between the parallel implementation of CRC-9 and its serial implementation. It also shows that parallel implementation uses less number of clock cycles than the serial implementation of CRC-9 thereby increasing the speed of the architecture. This paper is implemented using Verilog hardware description language, simulated using Xilinx ISE tools and synthesized using Cadence tools.

High Performance Table-Based Algorithm for Pipelined CRC Calculation

In this paper, we present a fast cyclic redun- dancy check (CRC) algorithm that performs CRC compu- tation for an arbitrary length of message in parallel. For a given message with any length, the algorithm first chunks the message into blocks, each of which has a fixed size equal to the degree of the generator polynomial. Then it computes CRC for the chunked blocks in parallel using lookup tables, and the results are combined together with XOR operations. In the traditional implementation, it is the feedback that makes pipelining problematic. In the proposed algorithm, we solve this problem by taking advantage of CRC's properties and pipelining the feedback loop. The short pipeline latency of our algorithm enables a faster clock frequency than previous approaches, and it also allows easy scaling of the parallelism while only slightly affecting timing. We build a Verilog implementation our pipelined CRC. The simulation results show that our approach is faster and more space- efficient than previous CRC implementations; with 256 bits input each clock cycle, our approach achieves about 36% throughput improvement with about 12% area reduction. Index Terms—Keywords: CRC, lookup table, pipelining

High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost

Parallel realization of the ATM cell header CRC

Parallel Cyclic Redundancy Check (CRC) implementations simultaneously process multiple bits of data in parallel, increasing the data processing rate, with only a relatively small increase in the hardware complexity of serial CRC implementations that process data bit serially. This paper develops octet (8 bit), 16 bit and 32 bit parallel realizations of two serial ATM cell header CRC circuits. We show that both octet parallel ATM cell header CRC implementations can perform CRC error detection at a speed of 4 to 6 times the data processing rate of equivalent serial implementations, with the 16 and 32 bit realizations yielding even greater improvement. We also explore other practical applications of these parallel realizations, such as cell header HEC generation and cell delineation. The circuit operation of the octet parallel CRC Register ATM cell header error detection circuit and octet parallel moving window Polynomial Divider ATM cell delineation circuit has been implemented and verified experimentally in the laboratory, with the circuit operation of all other parallel realizations verified in simulation using MAX+plus II.