Cyclic Redundancy Check Computation Research Articles

An Efficient Parallel CRC Computing Method for High Bandwidth Networks and FPGA Implementation

A cyclic redundancy check (CRC) is a widely used technique in data communication for detecting data transmission errors. However, existing FPGA-based parallel CRC hardware implementation schemes often face problems of excessive resource utilization and timing convergence difficulties in high-bandwidth networks. In addition, these problems are further exacerbated by the variable length of the end of the checksum data frame during data transmission. To address these challenges, this paper proposes a parallel CRC computation method based on precomputed seed values for bit-width normalization (named PSV-WN-CRC). The algorithm selects the corresponding primitive seed value according to the length of the data frame tail and converts the CRC computation with arbitrary bit-width to the CRC computation with fixed bit-width, thus adapting to the case of the indefinite length of the data frame tail. Based on this algorithm, this paper designs an efficient parallel CRC circuit on FPGA to reduce the consumption of resources. The experimental results show that the CRC algorithm and circuit proposed in this paper implemented on Virtex UltraScale+ FPGAs with 1024-bit wide CRC consumes only 5981 LUTs and achieves a maximum throughput of 392.2 Gbps. The method effectively reduces the resource consumption and improves the maximum throughput as compared to three advanced works.

Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput

With the rapid advancement of radiation hard imaging technology, space-based remote sensing instruments are becoming not only more sophisticated but are also generating substantially more amounts of data for rapid processing. For applications that rely on data transmitted from a planetary probe to a relay spacecraft to Earth, alteration or discontinuity in data over a long transmission distance is likely to happen. Cyclic Redundancy Check (CRC) is one of the most well-known package error check techniques in sensor networks for critical applications. However, serial CRC computation could be a bottleneck of the throughput in such systems. In this work, we design, implement, and validate an efficient hybrid look-up-table and matrix transformation algorithm for high throughput parallel computational unit to speed-up the process of CRC computation using both CPU and Field Programmable Gate Array (FPGA) with comparison of both methods.

Parallel Computation of CRC Using Special Generator Polynomials

CRC (Cyclic Redundancy Check) is an error detection method commonly used in data communication systems, computer networksand storage environments. In this method, the transmitter divides the message by an agreed upon polynomial called the generator and concatenates the calculated residue to the message. The properties of the generator determine the range of errors which are detectable in the receiver side. The division operation is currently performed using serial circuits called Linear Feedback Shift Registers especially in the Ethernetnetwork access protocol. Developing methods for parallel computation of the residue makes CRC suitable for higher layer protocols and software applications. This paper studies a case for parallel CRC computation using special generators which have special multiples called OZO (One-Zero-One) polynomials are divisible. We first provide a system atic approach to finding such polynomials and then design and evaluate the algorithm and the hardware required to perform the parallel division.

Multi-processor based CRC computation scheme for high-speed wireless LAN design

Presented is a software cyclic redundancy check (CRC) parallel computation scheme for the realisation of a high-speed wireless communication system on a multi-processor design platform. The proposed CRC generation scheme was applied to the IEEE 802.11n WLAN system. As a result, the proposed CRC scheme is capable of meeting tight latency constraint to achieve 144 Mbit/s throughput at a processor frequency less than 200 MHz, when evaluated with register-transfer-level simulation.

A universal algorithm for parallel CRC computation and its implementation

Derived from a proposed universal mathematical expression, this paper investigates a novel algorithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computations is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.

Fast and flexible CRC calculation

An algorithm for software or hardware implementation is presented, allowing fast computation of cyclic redundancy checks with arbitrary polynomials and a high flexibility, such as updating of checksums after modifying data block parts with a known old checksum.

Word-parallel CRC computation on VLIW DSP

Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances, a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using the full power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method is at least four times faster for 8, 16 and 32 bits CRC.

Computation of cyclic redundancy checks via table look-up

Cyclic Redundancy Check (CRC) codes provide a simple yet powerful method of error detection during digital data transmission. Use of a table look-up in computing the CRC bits will efficiently implement these codes in software.

On the computation of cyclic redundancy checks by program

On the computation of cyclic redundancy checks by program