Cycle-accurate Simulation Model Research Articles

Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs

High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and Digital Signal Processing (DSP) image processing accelerators. Unfortunately, HLS is a single process (component) synthesis method. Thus, the integration of these accelerators has to be performed at the RT level (Verilog or VHDL). This implies that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS. To address this, this work presents a methodology to generate entire heterogeneous SoCs in C. This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of synthesizable bus interfaces that allow any component in the system to send or receive data through the bus. Moreover, this work investigates the generation of processors and interfaces (peripherals) at the behavioral level as these are important parts of any SoCs, but have long been thought not to be efficiently synthesizable using HLS. Generating complete SoCs in C has significant advantages over traditional approaches. First, it enables the generation of fast cycle-accurate simulation models of the entire SoC, making the verification faster and easier. Second, it allows completely isolating the bus implementation details from the developers’ view, allowing the change between bus protocols with only minor changes in the designers’ code. Thirdly, it allows generating different SoC variants quickly by only changing the HLS synthesis options. Experimental results highlight these benefits.

FLASH: Fast, Parallel, and Accurate Simulator for HLS

A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL simulation environment often creates a barrier for those who are not field-programmable gate array (FPGA) experts. Moreover, such a low-level simulation takes a long time to complete. Software HLS simulators can help bridge this gap and accelerate the simulation process; but their shortcoming is that they do not provide performance estimation. To make matters worse, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve these performance estimation and correctness problems while maintaining the high speed of software simulators, this article proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. The experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.

A Bandwidth Control Arbitration for SoC Interconnections Performing Applications with Task Dependencies.

Current System-on-Chips (SoCs) execute applications with task dependency that compete for shared resources such as buses, memories, and accelerators. In such a structure, the arbitration policy becomes a critical part of the system to guarantee access and bandwidth suitable for the competing applications. Some strategies proposed in the literature to cope with these issues are Round-Robin, Weighted Round-Robin, Lottery, Time Division Access Multiplexing (TDMA), and combinations. However, a fine-grained bandwidth control arbitration policy is missing from the literature. We propose an innovative arbitration policy based on opportunistic access and a supervised utilization of the bus in terms of transmitted flits (transmission units) that settle the access and fine-grained control. In our proposal, every competing element has a budget. Opportunistic access grants the bus to request even if the component has spent all its flits. Supervised debt accounts a record for every transmitted flit when it has no flits to spend. Our proposal applies to interconnection systems such as buses, switches, and routers. The presented approach achieves deadlock-free behavior even with task dependency applications in the scenarios analyzed through cycle-accurate simulation models. The synergy between opportunistic and supervised debt techniques outperforms Lottery, TDMA, and Weighted Round-Robin in terms of bandwidth control in the experimental studies performed.

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

This work introduces a runtime system level method to detect hardware Trojan in third party behavioral intellectual properties (3PBIPs). Most of the HW Trojan detection techniques either rely on golden Trojan-free (trusted) models, which are compared to the suspected model, or source IPs with the same functionality from different vendors. In the case of BIPs, this is extremely hard, as it is a market still in its infancy. Moreover, it is very difficult to find HW Trojan at the system level as the trigger condition might be visible only when the system is fully functional. Thus, this work proposes the inclusion of a small HW Trojan detection circuit called trust filters to detect HW Trojan at runtime. With the help of cycle-accurate simulation model, it is possible to fine tune these filters so that the overall system has no performance degradation. This can be achieved by exploiting the slack time between the time that a slave returns the data to the master and the time that the master sends new data to the slave. The advantages of using C-based design are multi-fold: (i) It allows the generation of fast cycle-accurate models to measure the exact slack of each BIP mapped as a loosely coupled Hardware Accelerator (HWAcc) slave and (ii) its ability to build the complete SoC using synthesizable Application Programming Interfaces (APIs) and hence allowing the fine tuning of these trust filters. Experimental results show that our proposed architecture is very efficient leading to no performance penalties in many cases and has very small area overhead.

On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems

Leading-edge VLSI systems, essentially multiprocessor systems-on-chip, have a wide range of components integrated together and operating in unison. They can be analyzed as flow networks in which the system performance depends on the bandwidth, transmission time, and queueing delay characteristics of the individual components, their connectivity and interactions, as well as the traffic patterns they encounter. The flow in various parts of the system must ideally be distributed so as to extract the maximum throughput possible with minimum end-to-end delays. Such an ideal distribution for flow networks has previously been obtained using simple electrical circuits. We demonstrate a similar methodology for typical VLSI systems and provide the necessary extensions of the theory. We empirically validate the methodology using a cycle-accurate simulation model as the reference. We find this methodology to supply better distributions in the average case and comparable distributions in the worst case as compared to standard search procedures such as random sampling and simulated annealing. The real strength is that it provides a speedup of several orders of magnitude, i.e., 3-5 orders in our experiments. Thus it is an elegant means for analyzing and optimizing the flow in VLSI systems, which can easily be incorporated into design procedures, compilers and on-chip modules for real-time allocations.

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

This paper presents a novel simulation-based approach which targets the performance estimation of cache coherence protocol implementations. Our approach allows to model a cache coherence protocol where coherence transactions take zero cycle and do not generate communication accesses, in the hope that it will provide a close lower bound on latency and traffic. The protocol modeling approach relies on cycle-accurate simulation models in which components can access instantaneously and transparently internal states of other components. Using this strategy, the access time and the traffic due to cache misses are taken into account as it would be on a multiprocessor system without cache coherence. However, the proposed approach still ensures that processors receive coherent data. We detail the implementation of this approach in a cycle accurate multiprocessor simulation environment. To show its effectiveness, we implement cache and memory models for two coherence protocols both with and without our omniscient cache coherence (OCC) proposal. We show with a formal method that this approach makes it possible to preserve the consistency models implied by the cache coherence protocols, and experimentally that the OCC strategy protocol gives a close lower bound on latency and traffic.