Detailed Routing is one of the most time-consuming steps of physical synthesis of ICs. Also, it is very challenging due to the complexity of the design rules that the router must obey. For some of these rules, if they are handled in a postprocessing step after routing, it may be impossible to avoid design rule violations. This requires that these rules are handled by the path search algorithm used in routing. Thus, we propose DRAPS, a design rule aware path search algorithm. DRAPS is an A*-interval-based fast path search algorithm which is aware of the via library, the minimal area rule and the cut spacing rule of vias belonging to the same path. Our experiments show that DRAPS reduces the design rule violation count by 96% on average, in comparison with a non-design-rule aware path search. Besides, we have compared our detailed routing system to two state-of-the-art academic routers (Dr. CU and TritonRoute) that were tested using ISPD18 benchmarks. Our router has presented, on average, 22% less runtime and 81% less design rule violations w.r.t. Dr. CU, which was the better of the compared routers.