Custom Integrated Circuits Conference Research Articles

Guest Editorial 2022 Custom Integrated Circuits Conference

This Special Issue of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of key articles presented at the 2022 Custom Integrated Circuits Conference (CICC), which was a hybrid event, with in-person and virtual sessions. This was the first IEEE Solid-State Circuits Society (SSCS) conference to come back from the COVID-19 pandemic as an in-person and virtual event.

The 44th Annual IEEE Custom Integrated Circuits Conference (CICC 2023) [Conference Reports

The 44th Annual IEEE Custom Integrated Circuits Conference (CICC 2023) [Conference Reports

Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices

Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T<500°C, for the integration of SiP Raised Sources & Drains (RSD) in the upper devices without degrading the electrical performances of the bottom ones. We also target a lowering of the RSD resistance and an increase of the electron mobility in the channel of NMOS devices thanks to tensile strain [2]. Such a know-how will be useful to minimize the contact resistance and fabricate other types of devices such as FINFETs or h-GAA (e.g. nano-sheet devices) with Si (110) surfaces.Experiments were carried out in an Applied Materials epitaxy reactor featuring (i) liquid precursor delivery, together with H2, N2 or He carrier gas capability, enabling the use of Cl2; (ii) “High Precision Temperature Control (HPTC)”, allowing excellent LT control and enabling flexible rotation speeds; (iii) “precision flow distribution PFD-III”, enhancing uniformity performances. Selective Epitaxial Growth (SEG) is usually obtained with “co-flow” processes at rather high temperatures (>600°C). Chlorinated precursors (SiH2Cl2 (+ GeH4) + HCl, typically) are then sent simultaneously into the growth chamber. At LT (<500C°C), HCl cannot decompose, however. To overcome those limitations, we used a Cyclic Deposition Etch (CDE) strategy, with non-selective depositions followed by selective chemical vapor etches, to obtain SiP SEG.This strategy allowed us to obtain high quality films, as shown in Fig.1. The Omega-2Theta scans around the (004) X-Ray Diffraction order for tensile SiP (t-SiP) layers grown at T < 500°C with different Phosphorus concentrations were indeed typical of monocrystalline layers, with well-defined and intense peaks together with numerous thickness fringes. The substitutional P contents in those ~ 60 nm thick t-SiP layers were in the 1.02% - 5.42% range. The good layer uniformity in terms of thickness and P content, over a 300mm wafer radius, is shown in figure Fig.2.These layers grown at T <500°C were smooth, as shown in Fig.3, with a 0.21 nm Root Mean Square (RMS) roughness for a 60nm thick Si:P layer, i.e. a value close to the typical RMS roughness for t-SiP layers grown at high temperature with a chlorinated chemistry.The electrical resistivity in various t-SiP layers is plotted in Fig.4 as function of the substitutional phosphorus concentration and for various growth temperatures in the 450°C – 525°C range. Reducing the temperature by 75°C halved the electrical resistivity. We were able to achieve a resistivity as low as 0.21 mOhm.cm for a t-SiP layer with 5.8% of P grown at 450°C.We then evaluated, at first on tests structures without gates, our process selectivity. A top view Scanning Electron Microscopy image of a t-SiP layer grown non-selectively, with numerous amorphous SiP nuclei on SiO2, is shown in Fig 5.a. After some careful optimization, we succeeded in having fully selective processes versus SiO2, as shown in Fig 5.b.We then tested such optimized processes on low density FD-SOI devices with 28 nm design rules. A top-view SEM image of transistors after such a growth is shown in Fig.6. The growth selectivity was excellent, with nitride spacers and hard masks as well as isolations free of a-SiP nuclei for 31 nm of t-SiP with 4.5% of P deposited in the Sources/Drains. The surface was smooth, with a RMS roughness as low as 0.30nm on active areas, as shown in Fig.7. Thanks to High Resolution Reciprocal Space Maps (HR-RSM), we measured a Phosphorus concentration of 4.5% for that SiP layer grown on SOI. The very high quality of that epitaxy layer, with well-defined thickness fringes, is obvious in Fig.8. Cross-sectional Transmission Electron Microscopy (TEM) images such as the one shown in Fig. 9 enabled us to confirm, at the nanoscale, the excellent quality of such layers in RSDs.To sum up, we were able to develop a tensile Si:P process which was shown to be selective, at a temperature lower than 500°C, against SiO2 and SiN. Such t-SiP layers were successfully integrated in the Sources/Drains regions of FD-SOI 28nm devices. The very low material resistivity and the high phosphorus content should yield, notably because of tensile strain, performant NMOS devices in the near future.[1] C. Fenouillet-Beranger et al., IEEE TED 68, 3142-3148 (2021)[2] V. Chan et al., IEEE 2005 Custom Integrated Circuits Conference 2005, pp. 667-674 Figure 1

Guest Editorial 2021 Custom Integrated Circuits Conference

This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of key articles presented at the 2021 Custom Integrated Circuits Conference (CICC), which for the second time in a row was fully virtual due to the coronavirus pandemic. Originally planned to be held in Austin, TX, USA, the unpredictability of COVID-19 quickly lead the conference organization to decide to (again) go for a fully virtual format from April 25 to 30, 2021. With all the experience of the previous year, where CICC was the first IEEE Solid-State Circuits Society (SSCS) conference to go virtual, and that of subsequent SSCS and other conferences, it was comparatively smooth sailing.

Women in Circuits [Guest Editorial

The fall 2022 issue of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IEEE Solid-State Circuits Magazine</i> , on “Women in Circuits (WiC),” follows the tradition of previous issues since 2017, enabling more exposure to female leaders through exposition of their work in circuits and systems on a variety of important topics or their personal life/career experiences. WiC is also committed to promoting female leaders and diversity in the IEEE Solid-State Circuits Society (SSCS) and (co)organizing a variety of events to serve our communities, such as mentorship events at different conferences, including the International Solid-State Circuits Conference (ISSCC), the IEEE Symposium on VLSI Technology and Circuits (the VLSI Symposium), the IEEE Custom Integrated Circuits Conference (CICC), and the IEEE Asian Solid-State Circuits Conference (A-SSCC), among others. The WiC Committee would like to encourage more people to participate in future events. The following SSCS members were asked to contribute to this issue.

Guest Editorial 2020 Custom Integrated Circuits Conference

This Special Issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS features expanded versions of key articles presented at the 2020 Custom Integrated Circuits Conference (CICC), one of IEEE’s first conferences to go fully virtual due to the corona virus pandemic, from March 22 to March 25, 2020. Originally planned to be held at Hyatt Boston Harbor, Boston, MA, USA, growing concerns related to COVID-19 and the impact on the community’s ability to travel to the conference lead the conference organization to make the tough decision in January 2020 to go for a fully virtual format. The dates and schedule of the conference remained unchanged.

Guest Editorial 2019 Custom Integrated Circuits Conference

This Special Issue of the IEEE Journal of Solid-State Circuits features expanded versions of key articles presented at the 2019 Custom Integrated Circuits Conference (CICC) held at Hilton, Austin, TX, USA, from April 14 to April 17.

Call for Papers IEEE Custom Integrated Circuits Conference

Call for Papers IEEE Custom Integrated Circuits Conference

An Adaptive and High Coding Rate Soft Error Correction Method in Network-on-Chips

The soft error rates per single-bit due to alpha particles in sub-micron technology is expectedly reducedas the feature size is shrinking. On the other hand, the complexity and density of integrated systems are accelerating which demand ecient soft error protection mechanisms, especially for on-chip communication. Using soft error protection method has to satisfy tight requirements for the area and energy consumption, therefore a low complexity and low redundancy coding method is necessary. In this work, we propose a method to enhance Parity Product Code (PPC) and provide adaptation methods for this code. First, PPC is improved as forward error correcting using transposable retransmissions. Then, to adapt with dierent error rates, an augmented algorithm for configuring PPC is introduced. The evaluation results show that the proposed mechanism has coding rates similar to Parity check’s and outperforms the original PPC.Keywords&#x0D; Error Correction Code, Fault-Tolerance, Network-on-Chip.&#x0D; References&#x0D; [1] R. Baumann, Radiation-induced soft errors in advanced semiconductor technologies, IEEETransactions on Device and materials reliability. 5-3 (2005) 305–316. https://doi.org/10.1109/tdmr.2005.853449.[2] N. Seifert, B. Gill, K. Foley, P. Relangi, Multi-cell upset probabilities of 45nm high-k + metal gateSRAM devices in terrestrial and space environments, in: IEEE International Reliability Physics Symposium 2008, IEEE, AZ, USA, 2008, pp. 181–186.[3] S. Lee, I. Kim, S. Ha, C.-s. Yu, J. Noh, S. Pae, J. Park, Radiation-induced soft error rate analyses for 14 nmFinFET SRAM devices, in: 2015 IEEE International Reliability Physics Symposium (IRPS), IEEE, CA, USA, 2015, pp. 4B–1.[4] R. Hamming, Error detecting and error correcting codes, Bell Labs Tech. J. 29-2 (1950) 147–160. https://www.doi.org/10.1002/j.1538-7305.1950.tb00463.x.[5] M. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBMJ. Res. Dev. 14-4 (1970) 395–401. https://www.doi.org/10.1147/rd.144.0395.[6] S. Mittal, M. Inukonda, A survey of techniques for improving error-resilience of dram, Journal ofSystems Architecture. 91-1 (2018) 11–40. https://www.doi.org/10.1016/j.sysarc.2018.09.004.[7] D. Bertozzi, et al., Error control schemes for on-chip communication links: the energy-reliabilitytradeo, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24-6 (2005) 818–831. https://doi.org/10.1109/tcad.2005. 847907.[8] F. Chiaraluce, R. Garello, Extended Hamming product codes analytical performance evaluation for low errorrate applications, IEEE Transactions on Wireless Communications. 3-6 (2004) 2353–2361. https://doi. org/10.1109/twc.2004.837405.[9] R. Pyndiah, Near-optimum decoding of product codes: Block turbo codes, IEEE Transactions onCommunications. 46-8 (1998) 1003–1010. https://www.doi.org/10.1109/26.705396.[10] N. Magen, A. Kolodny, U. Weiser, N. Shamir, Interconnect-power dissipation in a microprocessor,in: Proceedings of the 2004 international workshop on System level interconnect prediction, ACM, Paris,France, 2004, pp. 7–13.[11] K. Dang, X. Tran, Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-ChipCommunication, in: Proceeding of 2018 IEEE 11th International Symposium on EmbeddedMulticore/Many-core Systems-on-Chip, IEEE, Hanoi, Vietnam, 2018, pp. 1–6.[12] L. Saiz-Adalid, et al., MCU tolerance in SRAMs through low-redundancy triple adjacent error correction, IEEE Transactions on VLSI Systems. 23-10 (2015) 2332–2336. https://www.doi.org/10.1109/tvlsi.2014.2357476.[13] W. Peterson, D. Brown, Cyclic codes for error detection, Proceedings of the IRE 49-1 (1961)228–235. https://www.doi.org/10.1109/jrproc.1961.287814.[14] S. Wicker, V. Bhargava, Reed-Solomon Codes and Their Applications, first ed., JohnWiley and Sons, NJ,USA, 1999.[15] I. Reed, X. Chen, Error-control coding for data networks, first ed., Springer Science and BusinessMedia, New York, 2012.[16] L. Peterson, B. Davie, Computer networks: a systems approach, fifth ed., Elsevier, New York, 2011.[17] K. Dang, et al., Soft-error resilient 3D Network-on-Chip router, in: 2015 IEEE 7thInternational Conference on Awareness Science and Technology (iCAST), China, 2015, pp. 84–90.[18] K. Dang, et al., A low-overhead soft–hard fault-tolerant architecture, design and managementscheme for reliable high-performance many-core 3D-NoC systems, The Journal of Supercomputing.73-6 (2017) 2705–2729. https://www.doi.org/10.1007/s11227-016-1951-0.[19] D. Ernst, et al., Razor: A low-power pipeline based on circuit-level timing speculation, in: The36th annual IEEE/ACM International Symposium on Microarchitecture, IEEE, CA, USA, 2003, pp. 10–20.[20] H. Mohammed, W. Flayyih, F. Rokhani, Tolerating permanent faults in the input port of the network onchip router, Journal of Low Power Electronics and Applications. 9-1 (2019) 1–11. https://www.doi.org/10.3390/jlpea9010011.[21] G. Hubert, L. Artola, D. Regis, Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFETtechnologies due to atmospheric radiation, Integration, the VLSI journal. 50 (2015) 39–47. https://www.doi.org/10.1016/j.vlsi.2015.01.003.[22] J.-s. Seo, et al., A 45nm cmos neuromorphic chip with a scalable architecture for learning in networks of spiking neurons, in: 2011 IEEE Custom Integrated Circuits Conference (CICC), IEEE, CA, USA, 2011, pp. 1–4.[23] NanGate Inc., Nangate Open Cell Library 45 nm. http://www.nangate.com, (accessed 16.06.16) (2016).

Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference

This Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of key papers presented at the 2018 Custom Integrated Circuits Conference (CICC), held in the DoubleTree Mission Valley in San Diego, CA, USA, April 8–11.

Guest Editorial 2017 IEEE Custom Integrated Circuits Conference

This Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of key papers presented at the 2017 IEEE Custom Integrated Circuits Conference (CICC), held in the Hotel Van Zandt in Austin, TX, USA, on April 30–May 3.

IEEE Custom Integrated Circuits Conference

IEEE Custom Integrated Circuits Conference

Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference

This special issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers from the 2015 Custom Integrated Circuits Conference (CICC), held in the DoubleTree Hotel in San Jose, California, USA, on September 28–30.

Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014)

The papers in this special section consists of expanded versions of six papers presented at the Custom Integrated Circuits Conference (CICC), held in San Jose, CA, USA, in September 2014.

Introduction to the Special Issue on the IEEE 2014 Custom Integrated Circuits Conference

The seventeen papers in this special issue were presented at the 2014 IEEE Custom Integrated Circuits Conference (CICC).

Guest Editorial&lt;newline/&gt;Special Section on the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013)

The twelve papers in this special section were presented at the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013)that was held in San Jose, CA, September 2013.

Introduction to the Special Issue on the 2013 IEEE Custom Integrated Circuits Conference

Introduction to the Special Issue on the 2013 IEEE Custom Integrated Circuits Conference

Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012)

This special section consists of expanded versions of seven papers presented at the Custom Integrated Circuits Conference, held in San Jose, California in September 2012.

Introduction to the Special Issue on the IEEE 2012 Custom Integrated Circuits Conference

This Special Issue of the IEEE Journal of Solid-State Circuits is comprised of 20 papers selected from the 2012 IEEE Custom Integrated Circuits Conference (CICC). The issue spans contributions in RF/wireless, high-speed I/O, and analog/mixed-signal including PLLs, data converters, power management, digital systems and analog techniques. The selected papers demonstrate state-of-the-art performance in power, area, or integration along with innovative circuit implementations and techniques.

Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011)

The eleven papers in this special section are expanded versions of papers presented at the Custom Integrated Circuits Conference (CICC 2011), held in San Jose, CA, in September 2011. The papers are grouped into three broad areas: analog,digital/memory, and RF circuits.