Custom Circuit Design Research Articles

Simulation of substrate coupling for mobile communications SoC – A 20 GHz VCO case study

An innovative substrate coupling simulation methodology with on-the-fly extraction and validation of CMOS substrate parasitic elements, combining boundary element method (BEM) with a computational python based physical layout extraction and RC modeling method, is presented in this work. The proposed methodology is seamlessly integrated into the standard virtuoso based custom circuit design flow and allows the designer to extract fast and accurate a substrate RC mesh, valid from DC to GHz, enabling crosstalk impact estimation and gaining insight on substrate coupling effects from the early stage of the design process until the prototype phase. The proposed substrate crosstalk modeling flow is validated using a 20 GHz VCO circuit as a crosstalk victim. The VCO vehicle is designed using a 65 nm RFCMOS process and the respective RF devices of the specific PDK are used. The PCB transmission line and the package parasitics must be considered as to achieve more accurate and realistic simulation results. The simulation scheme is set using a layout footprint test case and two separate signal injection tap points, each at a certain distance from the VCO victim. This simulation scheme can provide various substrate signal crosstalk scenarios by injecting signals that consist of multiple frequencies into the substrate. Three simulation analysis types, Transient, QPSS and ENVLP, are performed as to be able to designate which analysis is the most suitable for crosstalk simulation in terms of simulation time, accuracy and compatibility. Finally, as a sanity check and methodology validation, crosstalk isolation trends with respect to the aggressor distance and the substrate signal frequency are extracted and compared with the State-of-the-Art results available in literature.

Flexible Circuits and Architectures for Ultralow Power

Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-V DD, multi-V DD, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.

Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM

IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout

An Integrated Educational Platform Implementing Real, Remote Lab-Experiments for Electrical Engineering Courses

This paper describes an Internet-based laboratory, named Remote Monitored and Controlled Laboratory (RMCLab) developed at University of Patras, Greece, for electrical engineering experiments. The key feature of this remote laboratory is the utilization of real experiments, in terms of instrumentation and under measurement circuits, rather than simulation or virtual reality environment. RMCLab’s hardware infrastructure contains multiple reconfigurable sub-systems (FPGAs), which can be enhanced by almost any analog expansion module. The main characteristics of this system include the versatility of the hardware resources, due to the dynamic reconfiguration potentiality and the low cost of the hardware components. Moreover, this system enables its users to test, in real time, their own custom circuit designs. The paper concludes with a specific example regarding an elementary circuit in digital electronics and a short statistical review of the RMCLab educational usage. RMCLab can be accessed via the web through http://www.apel. ee.upatras.gr/rmclab.

Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

A 1.3-GHz fifth-generation SPARC64 microprocessor

A fifth-generation SPARC64 processor is fabricated in 130-nm partially depleted silicon-on-insulator CMOS with eight layers of Cu metallization. At V/sub dd/ = 1.2 V and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> = 25°C, it runs at 1.3 GHz and dissipates 34.7 W. The chip contains 191 M transistors with 19 M logic circuits in an area of 18.14 mm × 15.99 mm and is covered with 5858 bumps, of which 269 are for I/O signals. It is mounted in a 1360-pin land-grid-array package. The 16-byte-wide system bus operates with a 260-MHz clock in single-data-rate or double-data-rate modes. This processor implements an error-detection mechanism for execution units and data path logic circuits in addition to on-chip arrays to detect data corruption. Intermittent errors detected in execution units and data paths are recovered via instruction retry. A soft barrier clocking scheme allows amortization of the clock skew and jitter over multiple cycles and helps to achieve high clock frequency. Tunability of the clock timing makes timing closure easier. A relatively small amount of custom circuit design and the use of mostly static circuits contributes to achieve short development time.

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology

The IBM eServer z900 microprocessor is a seventh-generation zSeries™ (formerly S/390®) CMOS design which has achieved 1.3-GHz operation. This paper describes the 0.18-µm bulk CMOS, seven-level copper metal process and the high-frequency circuit, integration, and design methodologies developed to achieve this operation. The microprocessor was floorplanned to closely mimic the flow of the microarchitecture pipeline and reduce the communication delay overhead between units. Novel circuit techniques were used in the implementation of the arrays and cache hit detection logic to save power and reduce circuit complexity without sacrificing performance. A four-dimensional gate library and novel synthesis algorithms were developed to yield synthesized control implementations with the performance characteristics of a fully custom circuit design.

Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters

Trends in complementary metal-oxide-semiconductor (CMOS) technology and very large scale integration architectures are causing interconnect to play an increasing role in overall performance, power consumption, and design effort. Traditionally, repeaters are used for driving long onchip interconnects. However, recent studies indicate that repeaters are using increasing area, power, and design resources and are inherently limited in how much they can improve the performance (Adler and Friedman, 1998), (Sylvester and Keutzer, 1999), (Cong and Pan, 1999). The unidirectionality of repeaters also limits their applicability in multisourced lines. This paper presents a new circuit called the Booster that compares favorably with repeaters for driving long lines in terms of area, performance, power, and placement sensitivity. Boosters also have the advantage of being bidirectional and providing a low impedance termination to improve signal integrity. Driver edge rates are reduced and peak power is drastically reduced compared to repeaters, thus, improving signal integrity and mitigating inductive effects. Boosters are shown to be more than 20% faster for driving a variety of interconnect loads over conventional repeaters in a 0.16-/spl mu/m CMOS technology. Boosters are typically inserted three times less frequently than repeaters for optimal performance, resulting in fewer boosters for driving the same interconnect lengths and, hence, saving on area, power, and placement effort. Computer-aided design tools for global interconnect synthesis need to support a wider variety of circuit techniques such as boosters. Other exotic circuit techniques such as differential, dynamic, or low-swing techniques require significantly more custom circuit design, noise analysis, extra timing signals, or extra power supplies and are, hence, cumbersome for automatic interconnect synthesis tools. In contrast, the proposed boosters can be inserted on lines in a straightforward manner much like repeaters. Based on analytical delay models, we derive rules for insertion and sizing of boosters that can easily be incorporated into an interconnect synthesis tool. We formulate design rules that determine: 1) the number of boosters needed; 2) their placements; and 3) device sizes for driving a given interconnect load. The primary objective function is minimizing delay and then area and power. Power analysis is slightly more complex than for repeaters so we present a systematic design approach. A placement sensitivity analysis comparing boosters and repeaters is used to study the effects of realistic placement constraints that arise in microprocessor floorplans. We conclude by discussing various design tradeoffs between repeater and booster-based interconnect designs. We then present other potential applications of boosters in domino logic designs, multisource/multisink buses, and field programmable gate array interconnection network designs in addition to conventional point-to-point interconnection lines.

Custom circuit design as a driver of microprocessor performance

This paper presents a survey of some of the most aggressive custom designs for CMOS processor products and prototypes in IBM. We argue that microprocessor performance growth, which has traditionally been driven primarily by CMOS technology and microarchitectural improvements, can receive a substantial contribution from improvements in circuit design and physical organization. We predict that in future microprocessor designs the floorplan and wire plan will be as important as the microarchitecture, more control logic will be structured and become indistinguishable from dataflow elements, and more circuits will be designed and analyzed at the level of single transistors and wires.

A single-chip universal cable set-top box/modem transceiver

A mixed-signal digital cable-TV transceiver IC containing two distinctly separate quadrature amplitude modulation (QAM) receivers and a single QAM modulator has been designed. An integrated 10-b analog-to-digital converter (AID) interfaces the first receiver directly to an analog signal. This receiver demodulates 4/16/32/64/128/256-QAM signals carrying the television programs or cable modem data with a variable symbol rate from 1 to 7 MBaud. A 6-b A/D is integrated to interface the second receiver to an analog signal. This receiver, used by cable operators for access control, demodulates quadrature phase shift keying (QPSK) signals with a variable symbol rate from 0.75 to 1.6 MBaud. The upstream modulator provides two-way communication required for interactive television or cable modem services. Capable of QPSK/16-QAM modulation with a variable transmission rate up to 25 Mb/s, the modulator also includes an integrated 10-b digital-to-analog converter to provide radio-frequency analog output from 0 to 65 MHz. Both receivers and the transmitter incorporate on-chip forward error correction compliant with multiple worldwide standards allowing global deployment. The carrier, phase, and timing recovery for each receiver is achieved with on-chip tracking loops. Adaptive decision feedback equalizers are incorporated to eliminate intersymbol interference. The transmitter incorporates preamble prepending and preequalization to facilitate reception. The device further integrates access control message separation, set-top box control circuitry, and a parallel microprocessor bus interface to boost system performance. The design employs a combination of semicustom and custom circuit design techniques for speed, mixed-signal performance, and layout density. Fabricated in a single poly, four-layer metal, 0.35-/spl mu/m standard CMOS process, the chip area is 64 mm/sup 2/. The device is packaged in a 256 tape ball grid array (TBGA), and dissipates 3 W at 3.3 V.

Programmable active memories: reconfigurable systems come of age

Programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAM's offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAM's, through the example of DECPeRLe-1, an experimental device built in 1992. PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions; no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in 1992. A technology shrink increases the performance gap between conventional processors and PAM's. By Noyce's law, we predict by how much the performance gap will widen with time.

Digital FIR filters for high speed PRML disk read channels

This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology.

The impact of custom and semi-custom integrated circuits on measurement system design

Reviews custom and semi-custom integrated circuit design and implementation procedures. The effect of integrated circuit technology on measurement system design and manufacture is described. Correlation-based measurement systems and machinery health monitoring systems are introduced as particular examples illustrating the benefits that can result from the application of this technology.

Speech communication meets the IC revolution

Rapid improvements in integrated circuit technology have made it possible for complex speech processing algorithms to be implemented in compact, real‐time, low cost circuits. In this session, the evolution of this technology will be traced from early discrete‐component systems up to current practice. In a complementary way, speech processing algorithms will be described structurally so as to reveal the opportunity for custom circuit designs. The session papers describe several such custom devices of wide utility for speech processing research and applications, including both speech analysis and synthesis. A projection of future integrated circuit capability will also be given.