Curvature-compensated Bandgap Voltage Reference Research Articles

A [formula omitted]104 dB PSRR and 1.86-ppm/[formula omitted] curvature-compensated bandgap voltage reference with improved voltage-self-regulating technology

A high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) with low temperature coefficient (TC) is proposed. The PSRR is enhanced by an improved voltage-self-regulation (VSR) technology which provides a low-impedance branch and negative feedback loop. Furthermore, a curvature compensation structure is proposed to reduce the TC by utilizing the curvature-corrected current (ICU). The proposed BGR supply voltage range is 2.5–3.6 V and its output voltage is 1.2 V. The results of the simulation using a standard 65 nm CMOS process with 3.3 V thick oxide device demonstrate that the line regulation of the proposed BGR is approximately 0.015 mV/V in the supply voltage range of 3–3.6 V. A TC of 1.86 ppm/∘C is obtained in the temperature range of -40∘C to 125∘C, and PSRR of -104 dB@DC are achieved. The active area of the proposed BGR is 0.063 mm2.

A 1.2-V 0.959-ppm/°C multi-section curvature-compensated bandgap voltage reference with trimming

This article introduces a high-precision and low temperature coefficient(TC) bandgap reference (BGR) with a 1.2 V output voltage after a novel digital trimming. A multi-section curvature compensation circuit alleviates the variation caused by the temperature dependence of the base emitter nonlinear voltage of bipolar transistors. The novel digital trimming technology is utilized to reduce the TC and improve the output voltage precision(VP) of the proposed the BGR. Designed and simulated in a 65 nm CMOS process with an active area of 0.037 mm2. Simulation results of the proposed the BGR demonstrates that its output voltage is 1.2 V, the best TC is 0.959 ppm/°C over a −40 °C to 125 °C temperature range and the power consumption of 138 μW under 3.3 V supply voltage at room temperature with trimming. In the supply voltage range of 1.8–3.4 V, the line regulation (LR) is 0.25%/V.

A 2.5 V, 2.56 ppm/°C Curvature-Compensated Bandgap Reference for High-Precision Monitoring Applications.

This work presents a high-precision high-order curvature-compensated bandgap voltage reference (BGR) for battery monitoring applications. The collector currents of bipolar junction transistor (BJT) pairs with different ratios and temperature characteristics can cause greater nonlinearities in ΔVEB. The proposed circuit additionally introduces high-order curvature compensation in the generation of ΔVEB, such that it presents high-order temperature effects complementary to VEB. Fabricated using a 0.18 µm BCD process, the proposed BGR generates a 2.5 V reference voltage with a minimum temperature coefficient of 2.65 ppm/°C in the range of −40 to 125 °C. The minimum line sensitivity is 0.023%/V when supply voltage varies from 4.5 to 5.5 V. The BGR circuit area is 382 × 270 μm2, and the BMIC area is 2.8 × 2.8 mm2.

A curvature-compensated bandgap voltage reference with a temperature coefficient trimming circuit

This paper presents an advanced topology of bandgap voltage reference (BGR) which consists of a novel curvature-compensated circuit and a current-mode trimming circuit. A positive-temperature-coefficient (positive-TC) nonlinear term is produced in the difference between the base-emitter voltages of two bipolar junction transistors (ΔVBE) to realize the high-order curvature compensation. The ΔVBE is generated by adding a negative-TC current into the bandgap core. Owing to the compensated ΔVBE, the BGR could be fine-tuned by an innovative current-mode trimming circuit which takes less area and achieves a larger trimming range. Benefiting from the trimming circuit, the PVT stabilities of proposed BGR are improved. Designed in a 0.18 μm HVCMOS process, the BGR occupies an active area of 267μm×226μm. The post-layout simulation results show the BGR reaches a low TC of 1.64 ppm/∘C in a wide range of -55 °C to 125 °C.

A 4.6-ppm/°C High-Order Curvature Compensated Bandgap Reference for BMIC

This brief presents a high precision high-order curvature-compensated bandgap voltage reference (BGR) with a 3.11-V output voltage for battery-management integrated circuits. The proposed circuit utilizes the exponential characteristics of the base current and the resistance between bases of bipolar transistors to perform corrections. The curvature of subthreshold-operating MOSFETs is considered to further compensate for high-order temperature effects over a wide temperature range of 170 °C. Test results for the proposed BGR fabricated utilizing a standard 0.18- ${\mu }\text{m}$ BiCMOS process demonstrate that its line regulation is approximately 0.31 mV/V in a supply voltage range of 4.2–6.0 V. with 4-bit trimming, a temperature coefficient of 4.6 ppm/°C is obtained in the range of −40 °C to 130 °C. The active area of the proposed BGR is 634 ${\times }$ 351 ${\mu }\text{m}$ .

A High Order Curvature-Compensated Bandgap Voltage Reference with a Novel Error Amplifier

This paper presents a bandgap voltage reference (BGR), utilizing high order curvature-compensated technique with the temperature dependent resistor. Based on an improved error amplifier, [Formula: see text]80[Formula: see text]dB power supply rejection (PSR) @1[Formula: see text]kHz is achieved without additional complicated circuits. The circuit is fabricated in a standard [Formula: see text]m CMOS process, consuming 50[Formula: see text][Formula: see text]A at 25[Formula: see text]C with a supply voltage of 3.3[Formula: see text]V. Simulation results show that the proposed BGR can achieve a temperature coefficient as low as 1.18[Formula: see text]ppm/[Formula: see text]C over the temperature range from [Formula: see text]C to 120[Formula: see text]C. Monte Carlo simulation and Experimental Results validate the design.

Design of a bulk-isolated bandgap reference with 3.7 ppm/°C TC in 0.35-μm triple-well CMOS process

ABSTRACTA bulk-isolated curvature-compensated bandgap voltage reference (BGR) compatible with triple-well CMOS technologies is presented in this paper. Verification results of the proposed BGR implemented in a 0.35-µm 3.3-V triple-well CMOS technology demonstrate that the BGR achieves a reference voltage of 220.4 mV with an average temperature coefficient (TC) of 3.7 ppm/°C in the −40 to 130°C range with 8-bit trimming. The measured current consumption and power supply rejection of the circuit are 33.15 µA and −69.51 dB at 100 Hz, respectively (VDD = 3.3 V). The circuit is capable of operating with supply voltages down to 2 V and its line regulation is 0.16%/V over a voltage range from 2 to 3.6 V. The root mean square output noise voltage in the 0.1–10 Hz frequency range is 2.54 µV. Moreover, measurement results show that the substrate noise sensitivity at the BGR output improved more than 30 dB for frequencies up to 50 kHz, thanks to the employed block bulk isolation strategy, although the effective improvement is expected to be more than 75 dB without the coupling from the electrostatic discharge diode in the I/O pad.

Novel high-PSRR high-order curvature-compensated bandgap voltage reference

This paper proposes a novel high-power supply rejection ratio (high-PSRR) high-order curvature-compensated CMOS bandgap voltage reference (BGR) in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvature- corrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T1.5 current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42×10−6/°C from −55 °C to 125 °C with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of −123.51 dB, −123.52 dB, −88.5 dB and −50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.

A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference

A novel high precision high order curvature-compensated bandgap reference (BGR) is presented in this paper designed using the subthreshold current of self-cascode transistors in standard digital 0.18µm CMOS process. Simultaneously its temperature coefficient is typically 4.6ppm/°C in the temperature range of -25 to 120°C with a supply current of 17.25µA. A power supply rejection ratio (PSRR) of -51dB is achieved while the layout area is no more than 0.0022mm2.

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 μm 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm2. Simulation and testing results show that the temperature coefficient is 13.7ppm/K with temperature ranging from −40 to 150 °C, the power supply rejection ratio is −98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.

A V/SUB be/(T) model with application to bandgap reference design

The authors discuss a new model for the V/SUB be/(T) characteristics of a bipolar transistor. A curvature-compensated bandgap voltage reference scheme based on this model is described. A CMOS circuit configuration to implement the compensation scheme is proposed. It may be suitable for such uses as high-resolution monolithic data acquisition.