Current-steering Architecture Research Articles

Adaptive Suppression Method of LiDAR Background Noise Based on Threshold Detection

Background radiation in the LiDAR detection field of view is complex and variable, and the background noise generated can easily cause false alarms in the receiver, which affects the effective detection of the system. Through the analysis of the influence of background radiation noise of LiDAR on the detection performance, an adaptive suppression method of LiDAR background noise is proposed. This method realizes the rapid suppression of background noise in the instantaneous field of view through an adaptive threshold adjustment of current steering architecture with a back-end digital-to-analog converter (DAC) correction based on the principle of constant false alarm rate (CFAR) control. Aiming at the problem of accurate noise detection and quantification in a very short time, a dynamic comparator is used to replace the traditional continuous comparator. While detecting the number of noise pulses, the measurement of the pulse duration of noise is realized, which improves the accuracy of short-time noise detection. In order to verify the actual effect of the adaptive method, experiments were carried out based on the team’s self-developed LiDAR. The experimental results show that the measured noise ratio of the adaptive mode by using this method is the lowest. Even at 12 a.m., the noise ratio of the point cloud obtained by the adaptive mode is 0.012%, compared with 0.08% obtained by the traditional mode, which proves that this method has a good ability to suppress background noise. The proportion of noise reduction of the adaptive mode is more than 80% compared with the traditional mode. It achieves noise suppression through hardware at each detection, and each adjustment can be completed within a single period of pulse detection. Therefore, it has great advantages in real-time detection compared with the back-end software noise reduction processing method, and it is suitable for the application of LiDAR in the complex background environment.

Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering DACs

This work presents analysis and calibration of interleaving and data timing errors that are encountered in modern times-2 interleaved digital-to-analog converters (DACs) with a current-steering (CS) architecture. Such errors corrupt the DAC output spectrum with spectral images that require calibration. We develop an analytical model for the interleaving and data timing errors that we understand are most significant and propose a calibration algorithm that treats all of them. Extensive simulations of the algorithm are made possible by leveraging the speed and accuracy of the analytical model. The algorithm is demonstrated on a commercially-developed 10-bit times-2 interleaved CS-DAC, operating at 40GS/s in 14nm CMOS.

Implementation of digital-to-analog converter through CP-based GaAs/GaSb nanowire GAA-TFET

Digital-to-analog converter (DAC) is the most critical circuit of any chip which limits system performance and consume much power. Therefore, the focus of this work is the DAC implementation using GaAs/GaSb-based charge plasma nanowire GAA-TFET which provide better ON current at reduced ambipolarity and hence, reduce power consumption. Also, the linearity of the proposed device is much better than Si TFET due to the absence of random dopant fluctuation and hence, improves DAC accuracy. The DAC implemented here is the R–2R and current steering architecture which is the first ever known work of a charge plasma-based hetero-material nanowire TFET. For the DAC implementation, Verilog A lookup table is created from the simulated results of this device from TCAD Silvaco and rest of the circuit simulation is carried out in Cadence. Finally, DAC performance metrics have been analyzed and found that efficiency of current steering has been drastically improved compared to R–2R architecture.

A 2 GS/s, 6-bit DAC for UWB Applications In 0.18 ㎛ CMOS Technology

To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 μm CMOS technology and the area is 975 μm☓775 μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW.

32-GS/s 6-bit DAC based on SiGe technology for IM-DD OFDM systems with non-uniform quantization.

In this paper, we design and fabricate a 32-GS/s 6-bit digital-to-analog convertor (DAC) based on SiGe technology. The DAC uses double sampling technique and segment current steering architecture to achieve high dynamic linearity. A corrector circuit is proposed to suppress the duty cycle error for linearity optimization. The spurious free dynamic range (SFDR) is above 31.5 dBc over the Nyquist bandwidth at the sampling rate of 32-GS/s. A full-rate input interface is integrated to realize data exchange with field-programmable gate array (FPGA). The experimental results show that the net data rate of 50-Gb/s orthogonal frequency division multiplexing (OFDM) signals with non-uniform quantization can be generated by the designed and fabricated DAC. The OFDM signal transmission over 10-km standard single mode fiber (SSMF) with 64-quadrature amplitude modulation (QAM) and 128-QAM formats have been successfully achieved.

A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX**Project supported by the National Natural Science Foundation of China (Nos. 61006027, 61176030), the Research Foundation of Key Laboratory of Analog Integrated Circuit (Nos. 9140C0902120C09034, 9140c090204130c09042), and the Fundamental Research Funds for the Central Universities of China (No. ZYGX2012J003).

A 2.5 GS/s 14-bit D/A converter (DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a “5+9” segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT (process, source voltage and temperature) corner is also presented. The 8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a “5-31” decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer (DDS) chip, and is implemented in a 0.18 μm CMOS technology, occupies 4.86 × 2. 28 mm2 including bond pads (DAC only), and the measured performance is SFDR > 40 dB (with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure (means return-to-zero or quad-switch structure is unutilized), this paper DAC's clock frequency (2.5 GHz) and higher output frequency SFDR (> 40 dB, up to 1 GHz) has some competition.

A 10-bit current-steering CMOS digital to analog converter

This paper proposed a 10-bit digital-to-analog converter consisting of a segmented current-steering architecture, with five different sizes of current source.The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 0.35μm 2P4M technology. The power consumption was approximately 7.9mW at the sample rate of 200MHz, and the supply voltage was 3.3V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.16 LSB and 0.13 LSB, respectively. The measured SFDR (spurious free dynamic range) was 45.3dB under a 1MHz sine waveform.This work presented a good performance compared with other researches in DNL, INL and power consumption.

A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit

In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal frequency of 250 MHz, while the power consumption is 11.6 mW.

Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems

This paper presents the circuit designs and measured performance of two ultrahigh-speed low-power 6-b digital-to-analog converters (DACs) using InP-based heterojunction bipolar transistors (HBTs) for beyond-100-Gb/s/ch optical transmission systems. The first design is based on an R-2R ladder-based current-steering architecture with a novel double-sampling technique that relaxes the speed restraints for the DAC and helps achieve ultrahigh-speed operation. The DAC with the double-sampling technique achieves an excellent sampling speed of up to 32 GS/s with low power consumption of 1.4 W. The second design is based on a new timing alignment technique. The DAC with the timing alignment technique operates at a sampling rate of 28 GS/s with very low power consumption of 0.95 W and achieves an excellent figure of merit (0.53 pJ per conversion step). It provides a clear multilevel modulated signal for QAM transmission and can be applied to beyond-100-Gb/s/ch optical transmission systems.

A 10-bit Low-Power Small-Area High-Swing CMOS DAC

The design and measurements of a prototype general purpose digital to analog converter for readout systems in high energy physics experiments are presented. The main goals for the proposed DAC are low power consumption, small die area and high-swing voltage output. The 10-bit DAC design is based on a current steering architecture which includes a high-swing class AB output amplifier. The prototype ASIC is fabricated using 2P-4M 0.35- ?m technology. Measurements of maximum differential (DNL) and integral (INL) nonlinearity both show 0.42 LSB. The total power consumption is below 0.6 mW while the core area is 0.18 mm2.

A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ƒt of 175GHz and a peak ƒmax of 260GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/−0.07 LSB and +0.27/−0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7dB for a sinusoidal output of 72.5MHz at a sampling rate of 13.5GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24GS/s are also obtained. The total power consumption is as low as 0.88W with a supply voltage of −4.0V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5bits or more.

A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-mum SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 Omega loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.

A 14-bit 1.8-V 20-mW 1-mm/sup 2/ CMOS DAC

A low-voltage low-power small-area and high-resolution digital-to-analog converter (DAC) for mixed-signal applications is Introduced. A binary weighted current steering DAC is a power-efficient architecture, because almost all the current taken from the supply is used for the output signal. The current steering architecture is also highly suitable for high-speed operation. Typically, the architecture suffers from poor linearity characteristics, but the problem can be prevented with a novel calibration method, where the currents generated for the most significant bits are fine tuned. As a result, a very compact and low-power solution can be implemented by using a low-voltage digital technology.