Current Multiplier Research Articles

Very Low Voltage CMOS Current Multiplier with Floating DC Level Shifters

A compact, wide dynamic range, four-quadrant analog CMOS current multiplier is presented. The use of floating DC level shifters (floating batteries) made by resistors and current sources allows low supply voltages while maintaining at the same time a large input range and low harmonic distortion. Measurement results for an experimental prototype in a 0.8 μm CMOS technology demonstrate on silicon the proposed technique.

Phase current modulation of switched reluctance motor to minimize torque ripple

This paper presents a simple technique to minimize torque ripple of a switched reluctance motor (SRM). The technique is based on the control of the sum of the square of the phase currents by using only two current sensors and analog multipliers. The control characteristics of the SRM drives are analyzed for operation of the motor in the linear region of its magnetic characteristics. The simulation and experimental results of the proposed method are given. The advantages and limitations of the proposed circuit are explained.

Compact low voltage four quadrant CMOS currentmultiplier

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 µm technology shows a linearity error lower than 0.9% for signal swings up to ±50 µA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz.

A novel technique to achieve unity power factor and fact transient response in AC-to-DC converters

This paper presents a novel power factor correction technique for single-phase boost type AC-to-DC converters in continuous conduction mode. Instead of using the inductor current or switching device current, in this paper, the diode current in the boost converter is used to formulate the duty ratio of the switch in a special way which makes the input current sinusoidal and in phase with the input voltage. To improve the dynamic performance and minimize the input current harmonic components, a new double-injection compensation method is employed in the voltage feedback loop. The power factor corrector has the following advantages: (1) operation with constant switching frequency; (2) elimination of input voltage sensing, error amplifier in the current loop and multiplier in the output voltage feedback loop; (3) minimal total harmonic distortion in the input current; (4) fast dynamic response of the output voltage loop; and (5) simple implementation of the control circuit. The principles of operation of the proposed control scheme are explained. Simulation and experimental results are presented to verify the feasibility of the control strategy.

Programming floating-gate circuits with UV-activated conductances

A programming technique for controlling the floating gates (FGs) in ultra-low-voltage (ULV) floating-gate circuits is presented. Simple ULV PG current-scaling and level-shifting circuits are discussed. The current scaling and level shifting are accomplished using only minimum sized transistors and floating capacitors. Floating-gate current multiplier and divider circuits are described. Measured results are provided,.

Optimal circuits for parallel multipliers

We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. V.G. Oklobdzija et al. (1996) suggested a new approach, the Three-Dimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to produce a minimum delay PPRT using full adders. This is done by carefully modeling the relationship of the output delays to the input delays in an adder and, then, interconnecting the adders in a globally optimal way. Oklobdzija et al. suggested a good heuristic for finding the optimal PPRT, but no proofs about the performance of this heuristic were given. We provide a formal characterization of optimal PPRT circuits and prove a number of properties about them. For the problem of summing a set of input bits within the minimum delay, we present an algorithm that produces a minimum delay circuit in time linear in the size of the inputs. Our techniques allow us to prove tight lower bounds on multiplier circuit delays. These results are combined to create a program that finds optimal TDM multiplier designs. Using this program, we can show that, while the heuristic used by Oklobdzija et al. does not always find the optimal TDM circuit, it performs very well in terms of overall PPRT circuit delay. However, our search algorithms find better PPRT circuits for reducing the delay of the entire multiplier.

AB class current mode multipliersfor programmable neural networks

The author proposes AB class current mode multipliers for use in low power VLSI neural networks and other applications. The analogue AB class building blocks for programmable weight synaptic connections of neuron cells are presented and discussed.

Toward Massively Parallel Design of Multipliers

Current efficient multipliers have computation delays that increase as O(log n), where n is the number of bits in the inputs. In fact, this asymptotic time complexity for multiplication cannot be improved if the fan-in of the circuits is bounded above by a constant independent of n. In this paper, we study the potential gain in the speed of arithmetic computation provided by massive parallelism (i.e., unbounded fan-in/fan-out) and examine the tradeoffs between the speed and the amount of hardware in large but restricted fan-in threshold circuits. Threshold circuits are chosen because the potential speed-up in AND-OR circuits for multiplication is minimal even if the fan-in is allowed to be arbitrarily large. It is well known in complexity theory that any arbitrary fan-in AND-OR circuit for multiplication of two n-bit integers must have ω(log n/log log n) computation delays if the circuit size is bounded by a polynomial in n. Threshold circuits, on the other hand, are more powerful and we present here threshold circuits for multiplication with fan-in bounded by m, size O(2 − d/2 n 2 m 1/(2 d −1) [formula]), and depth O( d log n/log m) for every fixed integer d > 0. Similar results are also shown for symmetric functions such as the parity. With the rapid advance of VLSI technology and the promise of large scale implementations of cheap and reliable threshold gates, our results could be used for the design of massively parallel high-speed multipliers.

Diffusion network architectures for implementation of Gibbs samplers with applications to assignment problems

In this paper, analog circuit designs for implementations of Gibbs samplers are presented, which offer fully parallel computation. The Gibbs sampler for a discrete solution space (or Boltzmann machine) can be used to solve both deterministic and probabilistic assignment (association) problems. The primary drawback to the use of a Boltzmann machine for optimization is its computational complexity, since updating of the neurons is typically performed sequentially. We first consider the diffusion equation emulation of a Boltzmann machine introduced by Roysam and Miller (1991), which employs a parallel network of nonlinear amplifiers. It is shown that an analog circuit implementation of the diffusion equation requires a complex neural structure incorporating matched nonlinear feedback amplifiers and current multipliers. We introduce a simpler implementation of the Boltzmann machine, using a "constant gradient" diffusion equation, which eliminates the need for a matched feedback amplifier. The performance of the Roysam and Miller network and the new constant gradient (CG) network is compared using simulations for the multiple-neuron case, and integration of the Chapman-Kolmogorov equation for a single neuron. Based on the simulation results, heuristic criteria for establishing the diffusion equation boundaries, and neuron sigmoidal gain are obtained. The final CG analog circuit is suitable for VLSI implementation, and hence may offer rapid convergence.

Realization of monolithic variable gyrators and their application to active filters

AbstractWith the development of IC and LSI technology, it is strongly desired that integration of the analog filter be realized. This paper proposes a method to construct the differential input voltage‐controlled current source (VCCS) and the differential input, differential output VCCS, using the conventional current multiplier type VCCS. The features of the proposed construction is that the VCCS characteristics can be varied by the control current and the transconductance is not affected by the absolute accuracy of the resistances as long as their relative accuracy is maintained.A method also is presented in which the conventional LC filter is simulated using the gyrators composed of the proposed circuits. Then, by adding a resistor‐controlled current source circuit, a circuit construction also is presented whose control current can be determined by an external resistor so that the characteristics of more than one VCCS can be controlled.To verify the effectiveness of the proposed method, the third‐order elliptic filter with a 0.25‐dB ripple is designed. As a result of computer simulation, it is verified that the characteristics change little by the ambient temperature of ‐10 to 60°C and that the cut‐off frequency changes little for ±12.5 percent variation of the supply voltage. Thus, it is shown that the analog filter can be integrated without using the tuning system which has often been employed.

A QP-Free, Globally Convergent, Locally Superlinearly Convergent Algorithm for Inequality Constrained Optimization

An algorithm is proposed for the minimization of a smooth function subject to smooth inequality constraints. Unlike sequential quadratic programming type methods, this algorithm does not involve the solution of quadratic programs, but merely that of linear systems of equations. Locally the iteration can be viewed as a perturbation of a quasi-Newton iteration on both the primal and dual variables for the solution of the equalities in the Kuhn-Tucker first order conditions of optimality. It is observed that, provided the current iterate is feasible and the current multiplier estimates are strictly positive, the primal component of the quasi-Newton direction is a direction of descent for the objective function. This fact is used to induce global convergence, without the need of a surrogate merit function. A careful “bending” of the search direction prevents any Maratos-like effect, and local superlinear convergence is proven. While the algorithm requires that an initial feasible point be available, the succe...

A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits.

Current multiplier for use with ultramicroelectrodes

Current multiplier for use with ultramicroelectrodes

Some observations on the plasma current multiplier system

The plasma current multiplier (PCM) system is analysed and it is shown that the current gain is linearly proportional to the resistance in the cathode circuit. It is suggested that the analysis could be used to calculate the sheath resistance at the plasma/metal wall interface. The experimental results show that the sheath resistance per unit area is essentially constant in the operating range of the PCM system.

Plasma current multiplication at high current levels

The plasma current multiplier, PCM, is a simple gas discharge device which has the capability of amplifying small cathode currents to large anode currents. Experimental results are presented for the current gain of a PCM operating on argon and covering a range of gas pressures and current levels. It is found that gain increases with pressure and decreases with current density. A theory is presented which explains the experimental observations. Gas rarefaction due to heating by the discharge electrons is found to play a dominant role in high current PCM operation.

Simple implementation of sampled-data filters using current multipliers, switches and capacitors

An approach is discussed for a simple implementation of sampled-data filters. The implementation uses m.o.s. current multipliers, switches and capacitors and is useful for the design of integrated m.o.s. analogue filters. Compared with other approaches, the filters designed with this method require smaller area, use no operational amplifiers and have no consumption of d.c. static power. An example is presented showing good agreement between experimental and theoretical results.

Emissionless power cathode

The combination of a weak rf discharge and a plasma current multiplier constitutes an effective dc power cathode which operates without electron emission, elevated materials temperature, or wall bombardment, etc. Such power cathodes may find application wherever filament cathode operation poses difficulties, as with reactive gases, or where filament replacement is undesirable.

Properties of the collisional plasma sheath with ionizations

A simple model of a collisional plasma sheath, with ionizing collisions included and in contact with a negative metal wall is proposed. A broad range of plasma sheath solutions is obtained and their properties are discussed. The characteristics of the abnormal glow discharge as well as the characteristic of the electrostatic probe, in the ion saturation region, are incidentally recovered. This theory is then applied to the study of current multiplication in electrical discharges. The properties of a plasma current multiplier are predicted, both in the low and high pressure regimes, and are found to be in general agreement with the observed operating characteristics reported elsewhere.

The importance of the counter current oxygen multiplier mechanism in maintaining retinal function in the teleost

1. 1. Within minutes after elimination of supra-atmospheric oxygen tensions posterior to the teleost retina by administration of acetazolamide, one observes characteristic changes in the electroretinogram (ERG) which have subsequently been associated with retinal hypoxia. 2. 2. In vitro inhibition of carbonic anhydrase by acetazolamide in the frog and teleost retina produced no changes in the ERG indicating the drug has no direct effect on the retina. 3. 3. In vitro studies also confirmed that the teleost ERG could not be maintained with the pO 2 at arterial levels, thus an oxygen counter current multiplier in addition to blood flow is essential for the normal function of the avascular teleost retina. 4. 4. The trout retina was found capable of recovering from chronic hypoxia of up to 48 hr duration .

Effect of acetazolamide on some hematological parameters and ocular oxygen concentration in rainbow trout

1. 1. Values for several hematological parameters are given for control and acetazolamide treated rainbow trout. 2. 2. Analyses of blood obtained 24 hr after acetazolamide treatment indicates that this carbonic anhydrase inhibitor had no effect on the O 2 dissociation curve for whole blood. 3. 3. Acetazolamide did cause an increase in red blood cell (RBC) volume and a significant decrease in the amount of oxygen carried per g of hemoglobin. 4. 4. The Root effect was observed in trout blood even in the presence of a pO 2 of 450 mm Hg and the absence of functional carbonic anhydrase. 5. 5. It was concluded that the rapid depletion of ocular pO 2 in trout eyes following acetazolamide treatment is not due to a decrease in the supply of oxygen to the counter current multiplier via the blood.