Current-mode Signal Processing Research Articles

New Z copy- current differencing transconductance amplifier active filter using FinFET transistor based current Mode Universal Filter

This research paper presents the design of an active current mode device named Z-copy- Current Differencing Transconductance Amplifier (ZC-CDTA) in conjunction with FinFET (Fin Field-Effect Transistor) transistors. An input bias current can be used to adjust its parasitic resistances at its two current input ports. It is ideal for use in current-mode signal processing, which is steadily more common than voltage-style signal processing, because it operates in current mode on all terminals. The suggested component was implemented using Finfet technology, and its performances were assessed using simulations using cadence tools and linear technology SPICE. They demonstrate the new active element's usage, with a maximum bandwidth of 300MHz. The highest power consumption is 1.01 mW, and the supply voltages can be as low as ±0.1 V. The low-power consumption and wide current range tuning of the suggested Zc-CDTA are achieved.

A power-efficient dynamic-time current mode comparator

This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedback-based inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clock-shaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successive-approximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 µm CMOS technology, and occupies a silicon area of 7834 µm2. The proposed current comparator consumes a power of 14 µW with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art.

A 2.2 nW Analog Electrocardiogram Processor based on Stochastic Resonance Achieving a 99.94% QRS Complex Detection Sensitivity.

This paper presents an ultra-low power electrocardiogram (ECG) processor that can detect QRS-waves in real time as the data streams in. The processor performs out-of-band noise suppression via a linear filter, and in-band noise suppression via a nonlinear filter. The nonlinear filter also enhances the QRS-waves by facilitating stochastic resonance. The processor identifies the QRS-waves on noise-suppressed and enhanced recordings using a constant threshold detector. For energy-efficiency and compactness, the processor exploits current-mode analog signal processing techniques, which significantly reduces the design complexity when implementing the second-order dynamics of the nonlinear filter. The processor is designed and implemented in TSMC 65 nm CMOS technology. In terms of detection performance, the processor achieves an average F1 = 99.88% over the MIT-BIH Arrhythmia database and outperforms all previous ultra-low power ECG processors. The processor is the first that is validated against noisy ECG recordings of MIT-BIH NST and TELE databases, where it achieves better detection performances than most digital algorithms run on digital platforms. The design has a footprint of 0.08 mm2 and dissipates 2.2 nW when supplied by a single 1V supply, making it the first ultra-low power and real-time processor that facilitates stochastic resonance.

Analog Compatible Logic Functions Using EXCCIIs and an Extended Application for Sigmoid Activation Function

This paper introduces the use of an extra X current conveyor (EXCCII) for realizing logic operations, suited for mixed signal design, without necessitating separate digital blocks. The NOR and OR logic functions are thus shown to be realized using the current-mode analog building block operable at a low voltage. The use of [Formula: see text][Formula: see text]V supply makes the new circuits operable at low voltage. The EXCCII bias current used in the design is 25[Formula: see text][Formula: see text]A. The input currents for defining logic 0 and logic 1 are, respectively, taken as 0[Formula: see text]mA and 0.5[Formula: see text]mA. The proposed circuits’ delay is found to be 10[Formula: see text]ns for low-to-high transition, while 2[Formula: see text]ns for high-to-low transition for NOR gate under capacitive loading conditions. The use of the current-mode approach makes the new proposed circuit apt for current-mode signal processing. The new proposed logic function circuits are compatible with analog circuits, thus providing an easy merger for mixed signal systems design, paving the way to a modular design approach. As an extended application in artificial neural networks, the proposed circuit is shown to generate a sigmoid activation function with convincing results. Several results are included by varying the reference current, and the circuit’s robustness aspect is also tested in the presence of fluctuation in the bias current of EXCCII. The novel approach of utilizing an analog building block for realizing digital functions is, therefore, verified with promising future applications.

A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques

Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.

Low-Power Channel Select Filters for DVB-H Receivers

Design and implementation of CMOS channel select filters for digital video broadcasting-handheld integrated direct-conversion receivers are presented. The filters are designed to fulfill selectivity requirements with optimized power consumption. The proposed filters are based on the current amplifier and the transresistance amplifier offering alternatives for current-mode and voltage-mode signal processing, respectively. Adopting one active element per biquad allows optimization of the power consumption, and hence, leads to significant improvement over the available solutions. The two filters were fabricated in a standard 0.18- ${ \mu }\text{m}$ CMOS technology and experimental results are provided.

A MOS translinear cell-based configurable block for current-mode analog signal processing

This paper, proposes a low-voltage/power, high-speed configurable analog block (CAB) for current-mode nonlinear computation. A novel MOS translinear cell (MTC), two local switch networks and PMOS-NMOS arrays are the basic building blocks of the proposed CAB. This MTC consists of two overlapped translinear loops using the MOS transistors operating in weak inversion region. The proposed CAB is capable to implement such current-mode analog computational processors as one- and four-quadrant multipliers, one- and two-quadrant dividers, squarer, full-wave rectifier (absolute-value), RMS to DC converter and much other. Post-layout plus Monte Carlo simulations of the proposed design with 0.18 µm (level-49 parameters) TSMC technology is performed that prove its superiority over some other advanced works and robustness against process, voltage and temperature variations. This superb feature plus many others, mostly, are due to the precise multilateral analysis and optimal compensate of mismatches and second order effects of the proposed circuit that led to proper selection of devices sizes and deliberate arrangement of the layout.

Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool

Abstract The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.

Reconfigurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation

A software-defined radio receiver that is suitable for intra-band carrier aggregation is demonstrated. The RF front-end frequency selectivity is enhanced by the combination of the passive mixer and a proposed reconfigurable transimpedance amplifier. High order bandpass filtering function with frequency notches can be achieved at the front-end. Current domain complex signal processing is explored to select and separate multiple channels concurrently. The receiver contains a variety of functional building blocks that can be connected in different ways to form various architectures. The fine-grained programmability of component parameters and reconfigurability of receiver schemes enable optimum performance under varying signal and blocker scenarios. A proof-of-concept CMOS chip fabricated in a 65 nm CMOS technology is presented that supports up to three-channel aggregation. The receiver operates at any frequency between 0.5 to 3 GHz. The frequency separation between the concurrent RF channels can be tuned anywhere between 0 to +100 MHz. The concurrent receiver scheme can also be explored to reject large near-band blockers for high dynamic range.

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors' knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC $$0.18\,\upmu \hbox {m}$$0.18μm CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of $$\pm 0.75\,\hbox {V}$$±0.75V to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, $$8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }$$8.2MHzf-3dB,89? phase margin, 137 dB CMRR, 13 $$\Omega $$Ω input impedance, $$89\,\hbox {M}\Omega $$89MΩ output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, $$6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }$$6.9MHzf-3db,131? phase margin and 96 dB CMRR, $$22\,\Omega $$22Ω input impedance, $$33\,\hbox {M}\Omega $$33MΩ output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.

Fundamentals of Modern RF Wireless Receivers: A Short Tutorial

i»?To be compliant with multistandard applications, the RF front end of a modern transceiver must satisfy several challenging tasks such as large operative bandwidth, low noise, and high linearity. Over the years, addressing such requirements has significantly changed the radio architecture toward an ultimate solution based on current mode signal processing and passive mixers. In this article, after a brief description of the typical structure of a wireless receiver, voltage and current mode signal processing will be compared showing why a fully current-mode approach is more suitable in deep-scaled CMOS technologies [1], [2].

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8V and using 0.18μm CMOS process parameters. The power consumption and the required chip area are only 0.5mW and 77.4μm×70.2μm, respectively.

Current-mode signal processing implementation in HV SoI integrated systems

The paper presents and discusses possibilities and potential of current-mode based signal processing in high-voltage (HV) integrated systems, including current-mode functional block implementation into signal path of HV voltage-mode circuits. The paper is mostly focused on analog circuitry, implemented with the use of SoI processes. Discussion is based on the range of circuit solutions previously devised by authors and presently combined to present cumulated potential of current-mode approach in high-voltage (HV) integrated circuits. Analysis of the referenced research conducted by the authors of the paper, points out that in HV integrated systems, there are application areas well suited for current-mode processing implementation rather than the classic voltage-mode approach. Simplicity and consistency of HV current-mode functional blocks are presented, along with fitness of current-mode circuits for convenient implementation into HV SoI integrated circuits, with very limited loss of operation quality as compared to corresponding low-voltage functional blocks. Means of implementing current-mode circuits into HV voltage-mode systems are discussed.

A Novel Approach for Realization of Higher Order Filter using Bipolar and MOS Current-Mirrors

In this paper, we have presented an approach to realize higher order current-mode filters using cascade technique of lower order filters realized using CMOS current-mirrors. This paper presents the realization of higher-order low-pass (LP) active current-mode filters using cascade technique of second and third order filters. Interest in current-mode (CM) filters has been growing due to the fact that current-mode devices have wider dynamic range, improved linearity, and extended bandwidth as compared to their voltage- mode counterparts. In the sub-micron era of semi-conductor technology, the minute structure of devices causes a high electric field and thus the power supply voltage is limited to a certain low value to protect the device from destruction. Current-mode signal processing is quite attractive for operation at high frequencies and low power supply voltage operation from the viewpoint of sub-micron era. The realized filters do not contain any resistors, therefore simplifying the pattern of integrated circuits and thus reducing the chip area and the cost. The proposed circuits presented in the paper using bipolar technology and CMOS technology were tested in SPICE using BJT model NR100N and PR100N and the MOS structure using 0.5µm CMOS process parameters provided by MOSIS (AGILENT) and the results thus obtained were in accordance with the theoretical values.

ACHIEVING A LINEAR DOSE RATE RESPONSE IN PULSE-MODE SILICON PHOTODIODE SCINTILLATION DETECTORS OVER A WIDE RANGE OF EXCITATIONS

We are developing a new dose calibrator for nuclear pharmacies that can measure radioactivity in a vial or syringe without handling it directly or removing it from its transport shield “pig”. The calibrator's detector comprises twin opposing scintillating crystals coupled to Si photodiodes and current-amplifying trans-resistance amplifiers. Such a scheme is inherently linear with respect to dose rate over a wide range of radiation intensities, but accuracy at low activity levels may be impaired, beyond the effects of meager photon statistics, by baseline fluctuation and drift inevitably present in high-gain, current-mode photodiode amplifiers. The work described here is motivated by our desire to enhance accuracy at low excitations while maintaining linearity at high excitations. Thus, we are also evaluating a novel “pulse-mode” analog signal processing scheme that employs a linear threshold discriminator to virtually eliminate baseline fluctuation and drift. We will show the results of a side-by-side comparison of current-mode versus pulse-mode signal processing schemes, including perturbing factors affecting linearity and accuracy at very low and very high excitations. Bench testing over a wide range of excitations is done using a Poisson random pulse generator plus an LED light source to simulate excitations up to ∼106 detected counts per second without the need to handle and store large amounts of radioactive material.

An MTL-Based Configurable Block for Current-Mode Nonlinear Analog Computation

A configurable analog block (CAB) architecture based upon the MOS translinear (MTL) principle is proposed. It is programmed to implement some current-mode nonlinear analog computational functions. The proposed CAB architecture consists of one cascoded MTL cell, a local switch network, and a pMOS array. The cascoded MTL cell implements one MTL loop that is reconfigurable and programmable using the switch network and the pMOS array. This CAB architecture is capable of implementing various frequently used nonlinear functions, such as squaring/inverse function, rectifying (absolute value), and square-rooting/geometric mean functions. The CAB has been fabricated in a 0.5- μm CMOS technology and verifies the concept. High capability and flexibility of the proposed CAB makes it suitable for current-mode analog computational and signal processing applications.

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18μm CMOS technology parameters and supply voltage of ±0.75V. Simulation results with HSPICE show low THD of −60dB at the output signal, very low impedance of 0.6Ω and 0.2Ω at the input and feedback ports respectively and high output impedance of 10MΩ. Moreover it can provide wide −3dB bandwidth of 15.5MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.

Low Voltage and Low Power Current-Mode Divider and 1/X Circuit Using MOS Transistor in Subthreshold

A new low-voltage and low-power CMOS current-mode circuit that can perform divide and 1/x function is presented. HSPICE simulation was used to confirm the functionality of the circuit. This circuit will be a useful sub-circuit for analog current mode signal processing in battery powered application especially in biomedical implants.

A Novel Resistor-Free Electronically Adjustable Current-Mode Instrumentation Amplifier

In this paper, a novel topology for implementing resistor-free current-mode instrumentation amplifier (CMIA) is presented. Unlike the other previously reported instrumentation amplifiers (IAs), in which input and/or output signals are in voltage domain, the input and output signals in the proposed structure are current signals and signal processing is also completely done in current domain benefiting from the full advantages of current-mode signal processing. Interestingly the CMRR of the proposed topology is wholly determined by only five transistors. Compared to the most of the previously reported IAs in which at least two active elements are used to attain high common-mode rejection ratio (CMRR) resulting in a complicated circuit, the proposed structure enjoys from an extremely simple circuit. It also exhibits low input impedance employing negative feedback principal. Of more interest is that, using simple degenerate current mirrors, the differential-mode gain of the proposed CMIA can be electronically varied by control voltage. This property makes it completely free of resistors. The very low number of transistors used in the structure of the proposed CMIA grants it such desirable properties as low-voltage low-power operation, suitability for integration, wide bandwidth etc. SPICE simulation results using the TSMC 0.18-μm CMOS process model under supply voltage of ±0.8 V show a high CMRR of 91 dB and a low input impedance of 291.5 Ω for the proposed CMIA. Temperature simulation results are also provided, which prove low temperature sensitivity of the proposed CMIA.

FULLY DIFFERENTIAL CURRENT BUFFERS BASED ON A NOVEL COMMON MODE SEPARATION TECHNIQUE

In this paper a novel common mode separation technique for implementing fully differential current buffers is introduced. Using the proposed method two high CMRR (Common Mode Rejection Ratio) and high PSRR (Power Supply Rejection Ratio) fully differential current buffers in BIPOLAR and CMOS technologies are implemented. Simulation results by HSPICE using 0.18μm TSMC process for CMOS based structures in 1.4V supply voltage and transistor models NUHFARRY and PUHFARRY for BJT based one in 1.6V supply voltage show CMRR of 32.9dB and 33.1dB for CMOS based and BJT based fully differential current buffers respectively. The proposed fully differential current buffers show PSRR- of 114dB and 116dB in CMOS and BIPOLAR technologies respectively while their PSRR+ are 100dB and 109dB respectively. The proposed common mode separation technique can also be arranged in partial positive feedback configuration to provide high current gain too. Simulation results of this configuration in CMOS technology, show current gain and CMRR of 20.86dB and 53.91dB respectively. The proposed method tends to be a fundamental technique in current mode signal processing capable to be much further improved and utilized.