Current-mode ADC Research Articles

A Monolithic Polarization Controller and Tracking Loop for Optical Interconnect Demonstrated on a 90 nm Silicon CMOS-Photonic Platform

We report, to the best of our knowledge, the first monolithically-integrated silicon CMOS-photonic co-designed polarization tracking circuit implemented in a 90 nm CMOS SOI process. The Polarization Splitter and Rotator (PSR) decompose the optical input into TE and TM component and rotate the TM component to TE mode. The directional couplers combine the two TE components from PSR into single optical output. The thermal phase shifters on the optical path maximize the final optical output. A feedback loop implemented with monitoring photodetector, current mode ADC and Finite State Machine (FSM), control the current mode DACs to adjust the current input of thermal phase shifter. The circuit tracks randomized polarization rotation across the Poincaré sphere, maximizes TE-mode optical power, and experimentally achieves a BER of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10^{-11}$</tex-math></inline-formula> with 10 Gb/s PAM-2 modulation.

A 128 × 128 Current-Mode Ultra-High Frame Rate ISFET Array With In-Pixel Calibration for Real-Time Ion Imaging.

An ultra-high frame rate and high spatial resolution ion-sensing Lab-on-Chip platform using a 128×128 CMOS ISFET array is presented. Current mode operation is employed to facilitate high-speed operation, with the ISFET sensors biased in the triode region to provide a linear response. Sensing pixels include a reset switch to allow in-pixel calibration for non-idealities such as offset, trapped charge and drift by periodically resetting the floating gate of the ISFET sensor. Current mode row-parallel signal processing is applied throughout the readout pipeline including auto-zeroing circuits for the removal of fixed pattern noise. The 128 readout signals are multiplexed to eight high-sample-rate on-chip current mode ADCs followed by an off-chip PCIe-based readout system on a FPGA with a latency of 0.15s. Designed in a 0.35 μm CMOS process, the complete system-on-chip occupies an area of 2.6×2.2[Formula: see text] with a pixel size of 18×12.5 μ[Formula: see text] and the whole system achieves a frame rate of 3000fps which is the highest reported in the literature for ISFET arrays. The platform is demonstrated in the application of real-time ion-imaging through the high-speed visualization of sodium hydroxide (NaOH) diffusion in water at 60fps on screen in addition to slow-motion playback of ion-dynamics recorded at 3000fps.

Current-mode 12-bit ADC for Low Power Consumption using 4-bit ADC in repetitive structure

Current-mode 12-bit ADC for Low Power Consumption using 4-bit ADC in repetitive structure

Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs

A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follower (FVF) which replaces the source follower input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lower currents and lower power dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS technology at a power supply of 1.8 V. Propagation delay, power dissipation, and power delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. For both the implementations of ADCs, performance parameters, namely, DNL, INL, missing codes, monotonicity, offset, and gain errors, have been evaluated.

A Hybrid AMOLED Driver IC for Real-Time TFT Nonuniformity Compensation

An active matrix organic light emitting diode (AMOLED) display driver IC, enabling real-time thin-film transistor (TFT) nonuniformity compensation, is presented with a hybrid driving method to satisfy fast driving speed, high TFT current accuracy, and a high aperture ratio. The proposed hybrid column-driver IC drives a mobile UHD $\left({{3840} \times {2160}} \right)$ AMOLED panel, with one horizontal time of ${7}.{7}\,{\upmu \text{s}}$ at a scan frequency of 60 Hz, simultaneously senses the TFT current for back-end TFT variation compensation. Due to external compensation, a simple 3T1C pixel circuit is employed in each pixel. Accurate current sensing and high panel noise immunity is guaranteed by a proposed current-sensing circuit. By reusing the hybrid column-driver circuitries, the driver embodies an 8 bit current-mode ADC to measure OLED $V$ – $I$ transfer characteristic for OLED luminance-degradation compensation. Measurement results show that the hybrid driving method reduces the maximum current error between two emulated TFTs with a 60 mV threshold voltage difference under 1 gray-level error of 0.94 gray level (37 nA) in 8 bit gray scales from 12.82 gray level (501 nA). The circuit-reused current-mode ADC achieves 0.56 LSB DNL and 0.75 LSB INL.

A Multi-bit High Speed Current Mode Analog to Digital Conversion Algorithm

This paper proposes a generic algorithm for k-bit Analog to Digital Conversion. The proposed algorithm is very fast method of conversion of an analog signal into k-bit digital output in a multi-bit parallel fashion. The algorithm employs m stages, each of which is capable of producing bits such that k/m bits are converted at the same time. Thus, this algorithm can be considered a k = n X m conversion method. The algorithm proposed has been tested for a 4-bit current mode ADC implementation. The simulations have been performed in 0.18μm CMOS technology at the supply voltage of 1.8V using P-SPICE.

DCD – The Multi-Channel Current-Mode ADC Chip for the Readout of DEPFET Pixel Detectors

The current-mode ADC chip-prototype for the readout of DEPFET particle pixel-detectors with high spatial resolution is presented. The planned application of these DEPFET detectors are vertex detectors for ILC and Belle II. The chip has 72 ADC channels. Every channel processes the input signals using two cyclic ADCs that operate in parallel. The cyclic ADCs are based on current-mode memory cells. The measured signal to noise ratio of one ADC is about 660 (fast ADC variant: 520) and its conversion time is 320 ns (fast ADC variant: 160 ns) in the case of 8-bit resolution. Redundant signed-digit cyclic conversion is used for automated digital error correction. One ADC-core occupies only 40 ?m × 55 ?m, its static power consumption is 0.96 mW. Besides the two ADCs, every channel contains a regulated cascode and two additional current-mode memory cells that allow double-sampling of the input signal. Due to the need for high radiation tolerance, the chip has been implemented in a 180 nm CMOS technology using enclosed NMOS gate layouts. Novel radiation-hard circuits have been used. The chip has also been used to read out a small DEPFET test matrix.

A novel current-mode multi-channel integrating ADC

A novel current-mode multi-channel ADC has been designed, fabricated, and characterized in a 0.5-μm bulk CMOS process. The ADC utilizes a Wilkinson architecture with current-mode comparators and is capable of supporting multiple channels with an input current range of 10---150 μA. The main blocks in the ADC include a current ramp generator with active current mirrors, multiple current comparators, and a 12-bit Gray code counter. A novel architecture Gray code counter supports high frequency counting. For sampling rates up to 10 kHz, measurement results are presented including integral nonlinearity and differential nonlinearity. A per-channel power consumption of less than 2 mW using a Wilkinson architecture with 4 channels was observed. This work represents the first published current-mode, multi-channel Wilkinson ADC.

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 μm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

Current-mode cyclic ADC for low power and high speed applications

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements. >