Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs

Veepsa Bhatia,Neeta Pandey

doi:10.1155/2017/8245181

Abstract

A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follower (FVF) which replaces the source follower input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lower currents and lower power dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS technology at a power supply of 1.8 V. Propagation delay, power dissipation, and power delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. For both the implementations of ADCs, performance parameters, namely, DNL, INL, missing codes, monotonicity, offset, and gain errors, have been evaluated.

Highlights

Current comparator circuit finds application in a wide variety of applications like nonlinear current mode signal processing and analog to digital converters (ADCs)
Numerous structures for current comparators have been put forth in the literature, of which the one proposed by Traff [9] (Figure 1(a)) can be considered a pioneering structure which adheres to all the characteristics desirable of a current comparator, namely, low input impedance, lowpower dissipation, and moderate speed of operation
The theoretical proposition is verified through SPICE simulations using 0.18 μm TSMC CMOS technology parameters and a supply voltage of 1.8 V

Summary

Introduction

Current comparator circuit finds application in a wide variety of applications like nonlinear current mode signal processing and analog to digital converters (ADCs). Numerous structures for current comparators have been put forth in the literature, of which the one proposed by Traff [9] (Figure 1(a)) can be considered a pioneering structure which adheres to all the characteristics desirable of a current comparator, namely, low input impedance, lowpower dissipation, and moderate speed of operation. It comprises a source follower input stage and a CMOS inverter. The proposed current comparator so developed has further been used to implement a 3-bit full flash and a two-step CM flash ADC

The FVF Cell

Proposed Current Comparator

Current Mode Flash ADC

Two-Step Flash ADC

C2 C3 C4 Encoder C5 C6 C7

Conclusion