Current Generator Circuit Research Articles

Experimental and Simulation Study of Pulse Current Generator

8/20 µs lightning pulse current generators (LPCG) used in testing surge arresters require a laborious production process that needs a high budget. An easily repairable, portable, and affordable test system with a maximum energy of 2.9 kJ and a voltage level of 24 kV that can alter its parameter values was described in this work. Simulation and experimental studies were carried out to investigate the effects of the resistor and coil elements in the Pulse Current Generator (PCG) circuit on the amplitude, front, and tail time of the pulse current. Most components of the experimental system were created using 3D printing technology with polylactic acid (PLA) material. The production costs were significantly reduced, according to equivalent pulse generators. Tests at different pulse currents and voltage levels were performed with the experimental system. Power capacitors may often fail due to overvoltage, switching, and partial discharge reasons. The high voltage (HV) power capacitors used in the pulse generator introduced in the study were obtained with the help of low voltage capacitor stacks. As a result, a less expensive, high-capacity capacitor system that is easily and quickly repairable in case of failure was achieved.

A 4-Channel Neural Stimulation IC Design With Charge Balancing and Multiple Current Output Modes.

This article proposes a neural stimulation integrated circuit design with multiple current output modes. In the cathodic stimulation phase and anodic stimulation phase, each output current waveform can be independently selected to either exponential waveform or square wave, so the stimulator holds four stimulation modes. To minimize the headroom voltage of the output stage and enhance the power efficiency of the proposed stimulator, we introduce the exponentially decaying current which is realized by the exponential current generation circuit in this work. It can enhance the longer duration of the stimulation pulse as well. In case the residual charge may cause harm to patients, a charge balancing technique is implemented in this work for all operation modes. The four-channel stimulator IC is implemented in a 180-nm CMOS process, occupying a core area of 1.93 mm2. The measurement results show that the proposed stimulator realized a maximum power efficiency of 91.3% and the maximum stimulation duration is 3 times larger than previous works. Moreover, even in exponential output waveform mode, the maximum residual charge in a single cycle is only 255 pC due to the proposed charge balancing technique. The experiment results based on the PBS solution also show that the stimulator IC can remove residual charges within 60 μs, and the electrode voltage remains stable within a safe range under multicycle stimulation.

Designing Photoelectric Sensor Module in Infrared Communication and Applying Wireless Sensor Network in Leakage Cable Detection

With technological advancement, Near-infrared (NIR) spectroscopy instruments have gradually entered people’s daily life and production with their unique performance. Therefore, it has a positive significance in researching NIR spectroscopy analysis technology. This work designs a refrigerating Lead Sulfide (PbS) NIR photoelectric sensor P2664-05 and its photoelectric signal conversion circuit. The converted voltage signal is used for subsequent circuit processing through the amplification and frequency selection circuit. The aim is to ensure the sensor’s corresponding detectable spectral wavelength, sensitivity, and signal-to-noise ratio are improved under low temperatures. To this end, the refrigeration current generation circuit is designed. The refrigerating temperature is set below −15 °C, and the refrigerating current is 500 mA. At the same time, it is necessary to monitor whether the sensor’s temperature state meets the system stability requirements during the refrigeration process. The designed sensor module is connected to the instrument system in the test, and the whiteboard without spectral absorption is scanned. The results show that the designed NIR sensor’s shortcomings in noise processing performance have been improved using a System on a Programmable Chip (SoPC) as a processor. An infrared communication node is designed using its built-in digital resources and TFDU infrared communication chip. The designed NIR sensor and communication node are added to the 485 bus to build a communication network. In leakage cable detection, the communication network has higher security, lower error rate, and lower power consumption.

A Compact Amorphous In-Ga-Zn-Oxide Thin Film Transistor Pixel Circuit With Two Capacitors for Active Matrix Micro Light-Emitting Diode Displays

In this paper, we propose a novel amorphous In-Ga-Zn-oxide (a-IGZO) thin film transistor (TFT) pixel circuit for pulse width modulation (PWM) driving active matrix micro light-emitting diode (μLED) displays. The proposed pixel circuit compensates for wavelength shifts according to gray level and threshold voltage (VTH) variation of TFTs with only two capacitors. This compact operation can be achieved by simultaneous compensation for VTH along with data input in the constant current generation (CCG) circuit and the PWM circuit, which consist the pixel. Since the VTH variation in TFTs is compensated, the proposed pixel circuit can supply a uniform and stable current to the μLED throughout all gray levels. The compensation accuracy was verified by HSPICE with an oxide TFT model based on the measurement data. In addition, we analyzed the optimization method to improve the PWM driving by controlling the electrical properties of TFT, and verified this approach by simulation.

Suppression of Dynamic Current Leakage in Avalanche S-Diode Switching Circuits

This work investigates the dynamic current leakage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${S}$ </tex-math></inline-formula> -diode, which is a GaAs-based avalanche switch doped with deep Fe acceptor traps. The dynamic leakage has negative effect on superfast switching parameters of this unique device, and here we suggest an original way of reducing the leakage by means of circuit design. It is shown that an additional bias for avalanche S-diode in the current pulse generation circuit forms a negatively charged layer of iron traps near the electron-injecting junction. As a result, the concentration of nonequilibrium electrons goes down, which leads to a decrease in leakage current by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 3$ </tex-math></inline-formula> -4 times, and a rise in S-diode switching voltage. The results were obtained in the experimental study and are approved by calculation.

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation.

In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement IDS-VGS characteristics but could not accurately implement IDS-VDS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the IDS-VGS characteristics but also the IDS-VDS characteristics. A hybrid inverter and an integrate and fire (I&F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.

Design of Solar Energy Photoelectric Storage Comprehensive Application Experimental Device

This experimental device is composed of the battery characteristics test of the solar cell, rotating and leveling of the solar panel, photoelectric complementary power supply, battery capacity display and charging/capacity and internal resistance test unit. The battery characteristics test unit includes variable resistance circuit, modulation circuit, LED drive circuit and light intensity measurement and display circuit design. The rotating and leveling of the solar panel unit includes wind and rain sensor input, master control of MCU, vertical axis rotation, horizontal axis swing rotation, voice warning and so on. The photoelectric complementary power supply unit includes the charge and discharge controller, inverter, DC/AC load and control circuit. In addition, the battery capacity display unit includes signal input, analog-to-digital conversion and LED display/voice alarm circuit design. The battery charging /capacity and internal resistance test unit includes voltage regulator, constant current generation circuit, voltage detection, display circuit and control circuit. In this paper, the experimental contents and methods which can be carried out by the device are designed. The experiment of the device has the characteristics of rich knowledge integration, strong comprehensiveness and a flexible combination of contents.

A novel tunable bandgap voltage and current reference generation circuit

This paper presents a CMOS based tunable bandgap voltage and current reference generation circuit. The proposed circuit is designed without using Bipolar Junction Transistors (BJTs) for Proportional-To-Absolute-Temperature and Complementary-To-Absolute-Temperature generation, thus eliminating the problem of implementing BJT in CMOS fabrication process. The proposed circuit is simulated in standard 180 nm CMOS technology. A constant reference voltage ( $$V_{ref}$$ ) from 850 mV to 1.14 V and a constant reference current ( $$I_{ref}$$ ) from 170 to 227 nA is generated for corresponding supply voltage ( $$V_{dd}$$ ) tuned from 1.5 to 2 V for low power applications with an extended temperature range from − 55 to 175 $$^{\circ }$$ C. The proposed circuit at $$V_{dd}$$ = 1.8 V has a Temperature Coefficient (TC) of 0.37 and 0.53 ppm/ $$^{\circ }$$ C for $$V_{ref}$$ and $$I_{ref}$$ respectively, with a total power consumption of 594 nW (at $$V_{ref}$$ = 1.02 V and $$I_{ref}$$ = 204.5 nA). A monte-carlo simulation of the design is done for 1000 samples. The monte-carlo simulation for $$\hbox {V}_{{ref}}$$ , $$\hbox {I}_{{ref}}$$ and TC is done across the $$\hbox {V}_{{dd}}$$ (i.e. $$\hbox {V}_{{dd}} = 2\,\hbox {V}$$ to 1.5 V).

Pulse current generator with improved waveform fidelity for high-voltage capacitively coupled plasma systems

This paper proposes a current source-type pulse generator circuit to improve load voltage waveforms by solving the voltage ringing problem of capacitively coupled plasma systems. The voltage source-type pulse power supplies used in the plasma industry have short-circuit currents and voltage ringing problems with capacitively coupled plasma loads. The current source-type pulse generator proposed in this paper can solve these problems. The proposed circuit consists of four detailed circuits: bias current generator, bias current modulator, slope current generator, and slope current modulator. They form two constant currents at the DC link, and output two pulse currents to the load. These output currents contribute to generating the plasma load voltage required by the capacitively coupled plasma process. The proposed circuit is verified by a PLECS simulator and a laboratory-scale hardware system. To check the improvement of the output waveform, a voltage source-type pulse generator and the current source-type pulse generator are tested under the same experimental conditions. The results are represented by load voltage and current waveforms. In addition, the entire system of the current source-type pulse generator is designed and verified by simulation and experimental results. The resulting output waveforms meet the process requirements, and the obtained results demonstrate that the proposed current source-type pulse generator circuit can be suitably used for capacitively coupled plasma loads.

A New Modular XRAM-Like Inductive High- Current Pulse Generator Circuit Topology

XRAM (MARX spelt back words) is currently a very important circuit for high current pulse generators. In our previous studies, an XRAM-like circuit was proposed based on multiple pulse transformer modules and a capacitor connected in parallel. Compared with the traditional XRAM circuit, the same number of inductive energy storage modules can be used to generate higher current pulses. This circuit is also capable to recover the residual energy and generate repetitive high-current pulses. However, this circuit topology requires more power electronic switches (three IGBT switches per pulse transformer module). In order to reduce the number of switches, by adding two IGBT switches in the capacitor module, a new modular XRAM-like circuit with reduced switches (one IGBT switch per pulse transformer module) is proposed in this paper. The change of the circuit topology makes the capacitor discharge the primary inductors of the pulse transformer in series during the residual energy recovery stage, instead of the parallel discharge in the previous circuit. This requires the closing time of the IGBT switch in each pulse transformer module ahead of the discharge start time of the capacitor. Working process of the proposed circuit was described in detail and simulations of a 12-module circuit were carried out to verify the circuit operation. Finally, the preliminary experimental results of a two-module laboratory prototype are presented. The results confirm the theoretical analysis and show the validity of the converter scheme.

Design of a Low Temperature Drift Bandgap Reference Circuit with Second-order Curvature Compensation

In order to improve the accuracy and stability of bandgap reference output voltage, a bandgap reference circuit with high power supply rejection ratio and low temperature drift is designed based on 0.18um BCD technology. Based on the traditional bandgap voltage reference structure, this paper designs a current mirror cascade and a prereference circuit to supply power to the bandgap reference, and achieves a high power rejection ratio. At the same time, a PTAT2 current generation circuit is designed to realize the second-order temperature compensation of the reference output voltage. The simulation results show that the power supply voltage is 5V, PSRR is - 80dB, the temperature changes from - 55°C to 125°C, and the reference voltage temperature coefficient is 4.27ppm /°C. The circuit is simple in structure and easy to integrate. It can be widely used in bandgap reference circuit design.

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm2. The obtained average reference current is 6 nA having a slope of 5.5pA/°C.

Analog Building Blocks Using QFGMOS Technique

In this paper, quasi-floating gate MOSFET (QFGMOS) based current divider and pseudo-exponential function generator circuits are proposed. The use of QFGMOS makes the proposed circuits suitable for low voltage/low power operation. The proposed circuits have lower power supply voltage requirement, lower power dissipation and lower THD than the existing circuits available in literature. Both the circuits have been designed and simulated in Cadence virtuoso analog design environment using 180 nm CMOS technology. The simulation results have also been presented to validate the performance of the proposed circuits.

On Optimization of a Current Generation Circuit

On Optimization of a Current Generation Circuit

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory**Project supported by the National Natural Science Fundation of China (No. 61376028).

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 °C.

Total harmonic distortion of an asymmetric quasi-sinusoidal current

This paper presents the correlation of factors that determine the quality of asymmetric quasi-sinusoidal output current and dynamic losses in the switches of the current generator circuit. The operating mode of the generator was obtained, especially of its power circuit elements, where combination of acceptable output current quality with relatively small dynamic losses in switches and mass-dimensional parameters of the inductor are provided. Achieved results can be used in designing this type of generators.

A 1 V, 380nW, Current Generator Circuit using Sub-Threshold Region of Operation of MOSFETs

A 1 V, 380nW, Current Generator Circuit using Sub-Threshold Region of Operation of MOSFETs

Effective Technique for Circuit and Waveform Parameter Extraction in Impulse Current Tests and Its Application

In this paper, an effective technique for circuit and waveform parameter extraction in an impulse current generation circuit is presented. The technique is derived from the integral form of an ordinary differential equation of which the solution corresponds to the functions of impulse current waveforms. Using an impulse current waveform collected from the experiment, the numerical integration and linear least-square approaches are also employed to determine circuit and waveform parameters. To verify the validity of the proposed technique, the proposed method has been utilized in some applications for waveform parameter evaluation and determination of the appropriate circuit parameters in the impulse current tests. Using the corrected parameters by the proposed method, the impulse current waveforms were precisely generated according to the standard requirement. The simulated results agree well with the experimental results. It is confirmed that the method is fairly highly accurate and very effective in computation cost due to no iteration requirement in the process of the parameter extraction. The technique is very useful in impulse current tests and helps test engineers select appropriate circuit components without trial-and-error approaches.

Modeling of a single-cycle current generator while forming a quasi-sinusoidal current

The paper presents the results of investigation of the influence of the output voltage magnitude on the operating frequency of the switch in the single-cycle quasi-sinusoidal current generator circuit. Analytical expressions for calculating the time parameters for transients in the circuit under given assumptions have been obtained. The results presented in the paper can be used in the design of converters of this type.

A 10 Gb/s Inductorless AGC Amplifier With 40 dB Linear Variable Gain Control in 0.13 $\upmu \text{m}$ CMOS

This work presents an inductorless, 10 Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator, and a novel exponential function generator for extended dB-linear performance. Third-order interleaved feedback technique is utilized in the current steering VGA stage to achieve 10 Gb/s operation without using on-chip inductors. A stagger-tuned switching architecture for CMOS exponential function generation is proposed to achieve a dB-linear gain control range of ${\sim}40\;\text{dB}$ with better than $\pm 1\;\text{dB}$ gain error. The relationship between tuning range and approximation error is analyzed and a novel current ratio generator circuit is proposed to implement the approximation functions in the current domain. The AGC circuit achieves a highest data rate of 10 Gb/s for ${2}^{31}{-}1$ PRBS input, maintaining $360\;\text{mV}_\text{p-p}$ constant differential output with a BER ${ for an input dynamic range of ${\sim}24\;\text{dB}$ (15–240 $\text{mV}_\text{p-p}$ ). Fabricated in IBM 0.13 $\upmu \text{m}$ CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding the output buffer) and occupies an active area of $0.4\;\text{mm}^{2}$ .