Current-driven Passive Mixer Research Articles

A Highly Flexible Passive/Active Discrete-Time Delta-Sigma Receiver

This paper presents a fourth-order discrete-time direct RF-to-digital Delta-Sigma receiver architecture for flexible receivers with a wide frequency range. The use of a current-driven passive mixer with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement of the RF amplifier. In addition, the reconfigurable passive/active loop filter offers a good compromise between power consumption, linearity, and dynamic range. The other important feature of the proposed architecture is the use of a sampling frequency that is a divisor of the LO frequency. This solves several problems such as the upmixing of quantization noise, the need to reconfigure the Delta-Sigma loop when changing the LO frequency, and the use of two independent clocks for the LO and the sampling frequency. The circuit was implemented using 65 nm CMOS technology. The I/Q Direct Delta-Sigma receiver has an RF bandwidth of 20 MHz and a sampling frequency of 400 MHz. Measurement results show a very high dynamic range of up to 80 dB with a peak SNDR of 46 dB for a power consumption of 46 mW at 800 MHz.

Quad-channel broadband compact multi-antenna GNSS down-converter for high-reliability navigation

Abstract A high-reliability broadband high-linearity down-converter for multi-antenna global navigation satellite system (GNSS) receiver is presented in this paper. Based on direction-of-arrival estimation, the multi-antenna GNSS receiver can separate the GNSS signals from the interfering signals and suppress harmful broadband radio frequency interferences. To drive the off-chip 50 Ω resistive load and meet the stringent requirements of linearity, a quad-channel down-converter with a broadband common-gate low-noise transconductance amplifier, current-driven passive mixer and novel bridge mode transimpedance driving amplifier have been proposed to contruct the multi-antenna receiver. The operating frequency of this down-converter is from 1.15 to 1.65 GHz, covering all bands for global positioning system (GPS), Beidou navigation satellite system (BDS), global navigation satellite system (GLONASS) and Galileo. The measured results show that the proposed quad-channel down-converter achieves +38 dBm output 3rd order intercept point (OIP3) and +17 dBm OP1dB (output-referred 1 dB compression point), 9.5 dB to 12.9 dB noise figure (NF) across the variable gain of 10 dB to 27 dB and approximately 47 dB channel isolation.

A Harmonic Rejection Strategy for 25% Duty-Cycle IQ-Mixers Using Digital-to-Time Converters

Due to the use of wide-band analog front-ends in order to cover the many different frequency bands used in Long Term Evolution (LTE), blocker signals received by the antenna may reach the mixer input. As a consequence, square-wave mixer implementations, as, e.g., the 25% duty-cycle current-driven passive mixer, may lead to the down-conversion of these blocker signals by their harmonic response. This contribution describes a harmonic rejection (HR) strategy, which modifies the local oscillator (LO) waveform of a 25% duty-cycle current-driven passive mixer, to suppress specific harmonics. Two HR control signal waveforms are proposed and their performance is evaluated by circuit simulations using a 28nm CMOS technology. By applying the proposed concept, the down-conversion of a blocker by the mixer’s $3^{\text {rd}}$ order harmonic response can be suppressed by more than 30 dB, and the receiver noise figure (NF) is improved by 21.1 dB for a blocker power of −5 dBm at the low-noise amplifier (LNA) input.

A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

A switched-capacitor-based low-power receiver for electrocardiogram and respiration rate detection

This paper presents an integrated switched-capacitor-based low-power fully-differential analog front-end (AFE) for simultaneously detecting electrocardiogram (ECG) and respiration rate (RR). A current-driven passive mixer is used to up-convert the RR signal, and a preamplifier including a driven-ground common-mode feedback (CMFB) loop amplifies both the ECG and modulated RR signals. The modulated RR signal is then down-converted to baseband to be further amplified and detected. Switched capacitors (SCs) are widely used in the proposed AFE to provide large time constants that are also easily adjustable via the clock frequency. The chip is highly programmable, which enables complex automatic gain control (AGC) algorithms based on using a microcontroller within the loop. The AFE was fabricated in the OnSemi $$0.5\,\upmu \hbox {m}$$ CMOS process. Both simulation and measurement results verify the functionality of the chip for measuring multiple biosignals, including ECG, RR, electromyography (EMG), and galvanic skin response (GSR). Performance metrics are competitive compared to the state of the art.

Interferer Rejection in Cognitive Radio Receiver Using Heterodyne Conversion and Active Feedback

Limited linearity and local oscillator (LO) harmonics mixing are two major issues that ultra-wideband receivers, and a cognitive radio (CR) in particular, are dealing with. Direct-conversion schemes, based on current-driven passive mixers, have shown to improve the linearity but unable to resolve the LO harmonic mixing problem. They are usually limited to third and fifth harmonics rejection or require a very complex and power hungry circuitry for a higher number of harmonics. This paper presents a heterodyne conversion scheme in the 180-nm CMOS technology for CR applications (54–862 MHz band) that robustly mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable state-of-the-art $\mathrm {IIP_{3}}$ of better than +10 dBm is achieved. Measurements show an average noise figure of 7.5 dB when the active feedback loop is OFF (i.e., in the absence of destructive interference) and of 15.5 dB when the feedback loop is active and a 0-dBm interferer is applied, respectively.

A Low-Power CMOS Receiver for 5 GHz WLAN

Mobile devices demand low-power WiFi receivers for extended battery lifetime. This paper presents the design of an 11.6-mW receiver including baseband channel selection filtering that targets the IEEE802.11a standard. A 1-to-6 on-chip transformer serves as a low-noise amplifier with zero power dissipation and high linearity while providing ESD protection and differential outputs. The co-design of the transformer and the passive mixers leads to an efficient front end. Realized in 65-nm CMOS technology, the prototype exhibits a noise figure of 6 dB and a sensitivity of -66 dBm at a data rate of 54 Mb/s from 5 GHz to 5.9 GHz. A new analysis of fully-differential current-driven passive mixers is also presented to facilitate the design of the front end.

A 900 MHz Zero-IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER of -11 dBm, and an Rx input IP3 of -2.3 dBm.

An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory

An intuitive current-driven passive mixer model is presented. Without using complex math, it provides a signal-transfer-function/noise description of a passive mixer when used in a wireless receiver (RX) chain driven by a transconductor and loaded by a low-pass baseband (BB). Exploiting a switched-capacitor approach, the model represents a useful tool for simple hand analysis and design. The case of a 25 $ \%$ -duty-cycle quadrature RX chain based on a transimpedance amplifier at BB is analyzed in detail and compared with simulations, showing good accuracy.

Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 and IIP3 numbers, and IQ crosstalk, are significantly lowered due to the operating principles of the 25% duty-cycle passive mixer. It is revealed that with an intelligent sizing of the design parameters, the 25%-duty-cycle-mixer-based receiver is superior in terms of linearity, noise, and elimination of IQ crosstalk.

Second-Order Intermodulation in Current-Commutating Passive FET Mixers

Amplitude-modulation detection in the mixer plagues the performance of the zero-intermediate-frequency receiver by downconverting the envelope of amplitude modulated blockers to baseband where the desired channel is after downconversion. Simple equations based on physical mechanisms of second-order intermodulation generation have been derived which can predict the IIP2 of the current-driven passive mixer accurately. Derived equations have been verified by SPECTRE and SPECTRE-RF simulations, and mixer optimization has been explained.

Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers

Properties of the current-driven passive mixer are explored to maximize its performance in a zero-IF receiver. Since there is no reverse isolation between the RF and baseband sides of the mixer, the mixer reflects the baseband impedance to the RF and vice versa through simple frequency shifting. It is also shown that in an IQ down-conversion system the lack of reverse isolation causes a mutual interaction between the two quadrature mixers, which results in different high- and low-side conversion gains, and unexpected IIP2 and IIP3 values. With a thorough and accurate mathematical analysis it is shown how to design this mixer and its current buffer, and how to size components to get the best linearity, conversion gain and noise figure while alleviating the IQ cross-talk problem.

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 $\mu$m CMOS

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 mum CMOS process and occupies an active chip area of 1.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of -12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.