Current Computer Architectures Research Articles

Mixed-Precision Cholesky QR Factorization and Its Case Studies on Multicore CPU with Multiple GPUs

To orthonormalize the columns of a dense matrix, the Cholesky QR (CholQR) requires only one global reduction between the parallel processing units and performs most of its computation using BLAS-3 kernels. As a result, compared to other orthogonalization algorithms, CholQR obtains superior performance on many of the current computer architectures, where the communication is becoming increasingly expensive compared to the arithmetic operations. This is especially true when the input matrix is tall-skinny. Unfortunately, the orthogonality error of CholQR depends quadratically on the condition number of the input matrix, and it is numerically unstable when the matrix is ill-conditioned. To enhance the stability of CholQR, we recently used mixed-precision arithmetic; the input and output matrices are in the working precision, but some of its intermediate results are accumulated in the doubled precision. In this paper, we analyze the numerical properties of this mixed-precision CholQR. Our analysis shows that by selectively using the doubled precision, the orthogonality error of the mixed-precision CholQR only depends linearly on the condition number of the input matrix. We provide numerical results to demonstrate the improved numerical stability of the mixed-precision CholQR in practice. We then study its performance. When the target hardware does not support the desired higher precision, software emulation is needed. For example, using software-emulated double-double precision for the working 64-bit double precision, the mixed-precision CholQR requires about $8.5\times$ more floating-point instructions than that required by the standard CholQR. On the other hand, the increase in the communication cost using the double-double precision is less significant, and our performance results on multicore CPU with a different graphics processing unit (GPU) demonstrate that the overhead of using the double-double arithmetic is decreasing on a newer architecture, where the computation is becoming less expensive compared to the communication. As a result, with a latest NVIDIA GPU, the mixed-precision CholQR was only $1.4\times$ slower than the standard CholQR. Finally, we present case studies of using the mixed-precision CholQR within communication-avoiding variants of Krylov subspace projection methods for solving a nonsymmetric linear system of equations and for solving a symmetric eigenvalue problem, on a multicore CPU with multiple GPUs. These case studies demonstrate that by using the higher precision for this small but critical segment of the Krylov methods, we can improve not only the overall numerical stability of the solvers but also, in some cases, their performance.

Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols

In current computer architectures, the communication performance between threads varies depending on the memory hierarchy. This performance difference must be considered when mapping parallel applications to processor cores. In parallel applications based on the shared memory paradigm, the communication is difficult to detect because it is implicit. Furthermore, dynamic mapping introduces several challenges, since it needs to find a suitable mapping and migrate the threads with a low overhead during the execution of the application. We propose a mechanism to detect the communication pattern of shared memory applications by monitoring cache coherence protocols. We also propose heuristics that, combined with our communication detection mechanism, allow the mapping to be performed dynamically by the operating system. Experiments with the NAS Parallel Benchmarks showed a reduction of up to 13.9% of the execution time, 30.5% of the cache misses and 39.4% of the number of invalidation messages.

Synthesizable Manycore Processor Designs with FPGA in Teaching Computer Architecture

Manycore processor architectures are currently very widely used in almost all computer systems. Furthermore, many computer science department have started to teach parallel programming on manycore system platforms. To best understand the parallel programming on those manycore processors, the classes on manycore processor architecture also have to be provided. However, most current undergraduate computer architecture classes have not yet provided. In this paper, we have design a manycore processor design using a conventional MIPS processor design that is considered as a standard processor architecture model in a traditional undergraduate computer architecture class. Synthesize manycore processor models are developed in 850 lines of Verilog-HDL together with simple parallel applications so students can understand the entire manycore processor design and can learn the basics of the manycore system including underlying communication architecture.

No Core CI calculations for light nuclei with chiral 2- and 3-body forces

The atomic nucleus is a self-bound system of strongly interacting nucleons. In No-Core Configuration Interaction calculations, the nuclear wavefunction is expanded in Slater determinants of single-nucleon wavefunctions (Configurations), and the many-body Schrödinger equation becomes a large sparse matrix problem. The challenge is to reach numerical convergence to within quantified numerical uncertainties for physical observables using finite truncations of the infinite-dimensional basis space. We discuss strategies for constructing and solving the resulting large sparse matrices for a set of low-lying eigenvalues and eigenvectors on current multicore computer architectures. Several of these strategies have been implemented in the code MFDn, a hybrid MPI/OpenMP Fortran code for ab initio nuclear structure calculations that scales well to over 200,000 cores. We discuss how the similarity renormalization group can be used to improve the numerical convergence. We present results for excitation energies and other selected observables for 8Be and 12C using realistic 2- and 3-body forces obtained from chiral perturbation theory. Finally, we demonstrate that collective phenomena such as rotational band structures can emerge from these microscopic calculations.

Special Section: 2012 Copper Mountain Conference

The Twelfth Copper Mountain Conference on Iterative Methods was held March 25--30, 2012, in Copper Mountain, Colorado. The meeting featured more than 150 presentations on a wide range of topics in scientific computing, including Krylov subspace methods, preconditioning techniques, multigrid methods, domain decomposition, graph partitioning, nonlinear solvers, algorithms for eigenvalue computations, iterative methods in optimization, and so forth. Similar to other recent Copper Mountain meetings, several talks dealt with implementation aspects on current computer architectures, such as GPUs. Other talks addressed aspects of discretization methods relevant to iterative solution. A number of talks covered iterative solution methods in applications including compressed sensing, neutronics, incompressible resistive magnetohydrodynamics (MHD), density functional theory, radiative transfer, ocean simulation, image processing, fluid mechanics, electromagnetics, and many more areas. One especially encouraging aspect of the 2012 conference was the very large proportion of student attendees (61 of a total of 182 participants), which bodes well for the future of the field. Howard Elman (University of Maryland) and Ray Tuminaro (Sandia National Laboratories) served as conference co-chairs. This was Howard's last Copper Mountain Conference as co-chair after having served in this capacity since the 2004 edition. On behalf of the entire Scientific Committee, it is a pleasure to extend to Howard sincere thanks for his service and exceptional contributions to the success of the conference over all these years. Management services were provided by Annette Anthony of Front Range Scientific Computations, Inc. The Conference gratefully acknowledges financial support from the U.S. Department of Energy, IBM, Lawrence Livermore National Laboratory, Los Alamos National Laboratory, Sandia National Laboratories, and the U.S. National Science Foundation. The Copper Mountain Conference is organized in cooperation with the Society for Industrial and Applied Mathematics (SIAM). Submissions to this special section were open to the scientific community, as advertised in advance on websites of the SIAM Journal of Scientific Computing and the Copper Mountain Conference. The 23 papers in this section give a broad picture of the field of iterative methods and related issues in scientific computing. The variety of topics covered by these papers mirrors the wide array of fields represented at the conference. There are papers on Krylov methods (both theory and implementation aspects), papers on algebraic preconditioners, papers on multigrid methods, papers addressing the numerical solution of non-standard problems involving partial differential equations (e.g., with fuzzy coefficients), and several papers focusing on the use of iterative techniques in applications ranging from the investigation of the microscopic world (electronic structure of materials) to that of the large-scale universe (astronomical imaging). Between these two extremes we find papers on neutron transport, MHD, radiative transfer, electromagnetics, incompressible flow, medical imaging, compressed sensing, finance, and ocean modeling. The guest editorial board worked very hard to insure a rigorous peer-review process while meeting deadlines. Special thanks are due to Mitch Chernoff (SIAM Publications Manager) and Brittni Holland (SIAM Editorial Associate) for their efforts on this special section. We believe that the papers collected in this special section demonstrate the ever-increasing role of iterative methods in the solution of challenging problems in a wide variety of scientific and engineering areas, as well as the need for continuing research in this important field. Michele Benzi Guest Editor Guest associate editors: Xiao-Chuan Cai, Iain Duff, Howard Elman, Kirk Jordan, Tim Kelley, Misha Kilmer, Sven Leyffer, Ira Livshits, Tom Manteuffel, Steve McCormick, Luke Olson, John Shadid, David Silvester, Ray Tuminaro, Homer Walker, Carol Woodward, Irad Yavneh

Spiking neuronal network simulation technology for contemporary supercomputers

Event Abstract Back to Event Spiking neuronal network simulation technology for contemporary supercomputers Moritz Helias1*, Susanne Kunkel2, Jochen Eppler3, Gen Masumoto4, Jun Igarashi5, Shin Ishii6, Tomoki Fukai5, Abigail Morrison2 and Markus Diesmann1 1 Inst of Neuroscience and Medicine (INM-6) Computational and Systems Neuroscience, Research Center Juelich, Germany 2 Functional Neural Circuits Group Albert-Ludwig University of Freiburg, Germany 3 Inst of Neuroscience and Medicine (INM-6), Computational and Systems Neuroscience, Research Center Juelich, Germany 4 High-Performance Computing Team, RIKEN, Computational Science Research Program Kobe, Japan 5 Laboratory for Neural Circuit Theory, RIKEN Brain Science Institute, Wako, Japan 6 Integrated Systems Biology, Laboratory Department of Systems Science, Graduate School of Informatics, Kyoto University, Japan Functional neuronal networks, like the visual cortex of primates, comprise on the order of 100 million neurons, consisting of areas that exceed 10 million neurons and 100 billion synapses. The memory demands of such simulations are only met by distributed simulation software and supercomputers, like the Jugene BG/P supercomputer in Juelich and the K computer in Kobe. Though connectivity between brain areas is sparse, there are fewer constraints within areas. A general simulation tool needs to be able to simulate networks of 10 million neurons with arbitrary connectivity, often assumed to be random. This presents the worst case scenario: Firstly, there is no redundancy that allows to compress the representation of synaptic connectivity. Secondly, communication between the compute nodes is potentially all-to-all. Here we quantitatively demonstrate the recent advances of neural simulation technology [2] on the example of the simulator NEST [1], which have lead to a readily usable tool for the neuroscientist. As the memory rather than run time limits the maximal size of a neuronal network, we explain the systematic improvements of the distributed data structures adapted to the sparse and random connectivity. High performance and good scaling of network setup and simulation are achieved with a hybrid code combining OpenMP threads and MPI, exploiting the multi-core architectures of K and Jugene. We parameterize and employ a model of memory consumption to estimate the machine size needed for a given neuroscientific question; a crucial tool not only to plan simulations, but also for computation time grant applications. Simulations of networks exceeding 10 million neurons on K and Jugene are shown to determine the limits of the current technology and computer architectures. Partially supported by the Helmholtz Alliance on Systems Biology, the Next-Generation Supercomputer Project of MEXT, EU Grant 269921 (BrainScaleS), the VSR computation time grant JINB33 on the JUGENE supercomputer, and by early access to the K computer at the RIKEN Advanced Institute for Computational Science. [1] Gewaltig M-O and Diesmann M (2007) NEST. Scholarpedia, 2(4):1430. [2] Kunkel S, Potjans TC, Eppler JM, Plesser HE, Morrison A and Diesmann M (2012) Front. Neuroinform. 5:35. doi: 10.3389/fninf.2011.00035 Keywords: Large scale modeling Conference: 5th INCF Congress of Neuroinformatics, Munich, Germany, 10 Sep - 12 Sep, 2012. Presentation Type: Poster Topic: Neuroinformatics Citation: Helias M, Kunkel S, Eppler J, Masumoto G, Igarashi J, Ishii S, Fukai T, Morrison A and Diesmann M (2013). Spiking neuronal network simulation technology for contemporary supercomputers. Front. Neuroinform. Conference Abstract: 5th INCF Congress of Neuroinformatics. doi: 10.3389/conf.fninf.2013.08.00012 Copyright: The abstracts in this collection have not been subject to any Frontiers peer review or checks, and are not endorsed by Frontiers. They are made available through the Frontiers publishing platform as a service to conference organizers and presenters. The copyright in the individual abstracts is owned by the author of each abstract or his/her employer unless otherwise stated. Each abstract, as well as the collection of abstracts, are published under a Creative Commons CC-BY 4.0 (attribution) licence (https://creativecommons.org/licenses/by/4.0/) and may thus be reproduced, translated, adapted and be the subject of derivative works provided the authors and Frontiers are attributed. For Frontiers’ terms and conditions please see https://www.frontiersin.org/legal/terms-and-conditions. Received: 21 Mar 2013; Published Online: 27 Nov 2013. * Correspondence: Dr. Moritz Helias, Inst of Neuroscience and Medicine (INM-6) Computational and Systems Neuroscience, Research Center Juelich, Jülich, Germany, m.helias@fz-juelich.de Login Required This action requires you to be registered with Frontiers and logged in. To register or login click here. Abstract Info Abstract The Authors in Frontiers Moritz Helias Susanne Kunkel Jochen Eppler Gen Masumoto Jun Igarashi Shin Ishii Tomoki Fukai Abigail Morrison Markus Diesmann Google Moritz Helias Susanne Kunkel Jochen Eppler Gen Masumoto Jun Igarashi Shin Ishii Tomoki Fukai Abigail Morrison Markus Diesmann Google Scholar Moritz Helias Susanne Kunkel Jochen Eppler Gen Masumoto Jun Igarashi Shin Ishii Tomoki Fukai Abigail Morrison Markus Diesmann PubMed Moritz Helias Susanne Kunkel Jochen Eppler Gen Masumoto Jun Igarashi Shin Ishii Tomoki Fukai Abigail Morrison Markus Diesmann Related Article in Frontiers Google Scholar PubMed Abstract Close Back to top Javascript is disabled. Please enable Javascript in your browser settings in order to see all the content on this page.

Large-scale ab initio configuration interaction calculations for light nuclei

In ab-initio Configuration Interaction calculations, the nuclear wavefunction is expanded in Slater determinants of single-nucleon wavefunctions and the many-body Schrodinger equation becomes a large sparse matrix problem. The challenge is to reach numerical convergence to within quantified numerical uncertainties for physical observables using finite truncations of the infinite-dimensional basis space. We discuss strategies for constructing and solving the resulting large sparse matrix eigenvalue problems on current multicore computer architectures. Several of these strategies have been implemented in the code MFDn, a hybrid MPI/OpenMP Fortran code for ab-initio nuclear structure calculations that can scale to 100,000 cores and more. Finally, we will conclude with some recent results for 12C including emerging collective phenomena such as rotational band structures using SRG evolved chiral N3LO interactions.

Special Section: 2010 Copper Mountain Conference

The biennial Copper Mountain Conference on Iterative Methods was held April 4–9, 2010. This meeting included more than 140 presentations covering many scientific computing areas, such as uncertainty quantification, optimization, Markov chains, saddle-point systems, inverse problems, direct factorizations, Krylov methods, algebraic multigrid, software frameworks, and advanced computer architectures. A partial list of the represented application domains included acoustic scattering, material science, circuit simulation, neutron transport, image processing, magnetohydrodynamics, and porous media flow. Howard Elman (University of Maryland) and Ray Tuminaro (Sandia National Laboratories) served as co-chairs. Management services were provided by Annette Anthony of Front Range Scientific Computations, Inc. The Conference is gratefully for financial support from the Department of Energy, IBM, Lawrence Livermore National Laboratory, Los Alamos National Laboratory, Sandia National Laboratories, and the National Science Foundation. The Copper Mountain Conference is organized in cooperation with the Society for Industrial and Applied Mathematics (SIAM). Submissions to this special section were open to the public. This was advertised in advance on web sites of the SIAM Journal on Scientific Computing (SISC) and the Copper Mountain Conference. The collection of papers in this section all center on iterative methods. However, many diverse topics are covered spanning contributions with a theoretical orientation to those that are more applied or driven by a specific application area. Additionally, several papers are highly influenced by current computer architecture trends. Some of the submissions also appeared in the student paper competition, a unique event at the Copper Mountain conferences that has proven to be a successful forum for presenting the latest results in the field. We have had increasingly strong participation from talented recent Ph.D. holders and current Ph.D. students in this competition. I wish to thank the guest editorial board, the SIAM/SISC staff, and the referees for their hard work to help meet deadlines. Special acknowledgment is due to Mitch Chernoff (SIAM Publications Manager) and Heather Blythe (SIAM Senior Publications Coordinator) for their efforts on this special section. We hope that this special section will continue to foster new developments in this important area of research. The diversity of topics clearly demonstrates the significant impact of iterative methods across many scientific computing areas and the need for continued research.

Top Picks from the 2008 Computer Architecture Conferences

The 12 articles in this special issue highlight the following key trends in current computer architecture design and research: the increased importance of thread-level parallelism; the increasing complexity of software and the need for architectures that improve programmability, analyzability, and correctness; the increasing urgency of controlling chip-wide power; and the emerging problem of process variation.

3D prestack plane-wave, full-waveform inversion

Prestack depth migration has been used for decades to derive velocity distributions in depth. Numerous tools and methodologies have been developed to reach this goal. Exploration in geologically more complex areas exceeds the abilities of existing methods. New data-acquisition and data-processing methods are required to answer these new challenges effectively. The recently introduced wide-azimuth data acquisition method offers better illumination and noise attenuation as well as an opportunity to more accurately determine velocities for imaging. One of the most advanced tools for depth imaging is full-waveform inversion. Prestack seismic full-waveform inversion is very challenging because of the nonlinearity and nonuniqueness of the solution. Combined with multiple iterations of forward modeling and residual wavefield back propagation, the method is computer intensive, especially for 3D projects. We studied a time-domain, plane-wave implementation of 3D waveform inversion. We found that plane-wave gathers are an attractive input to waveform inversion with dramatically reduced computer run times compared to traditional shot-gather approaches. The study was conducted on two synthetic data sets — Marmousi2 and SMAART Pluto 1.5 — and a field data set. The results showed that a velocity field can be reconstructed well using a multiscale time-domain implementation of waveform inversion. Although the time-domain solution does not take advantage of wavenumber redundancy, the method is feasible on current computer architectures for 3D surveys. The inverted velocity volume produces a quality image for exploration geologists by using numerous iterations of waveform inversion.

Mesh Layouts for Block-Based Caches

Current computer architectures employ caching to improve the performance of a wide variety of applications. One of the main characteristics of such cache schemes is the use of block fetching whenever an uncached data element is accessed. To maximize the benefit of the block fetching mechanism, we present novel cache-aware and cache-oblivious layouts of surface and volume meshes that improve the performance of interactive visualization and geometric processing algorithms. Based on a general I/O model, we derive new cache-aware and cache-oblivious metrics that have high correlations with the number of cache misses when accessing a mesh. In addition to guiding the layout process, our metrics can be used to quantify the quality of a layout, e.g. for comparing different layouts of the same mesh and for determining whether a given layout is amenable to significant improvement. We show that layouts of unstructured meshes optimized for our metrics result in improvements over conventional layouts in the performance of visualization applications such as isosurface extraction and view-dependent rendering. Moreover, we improve upon recent cache-oblivious mesh layouts in terms of performance, applicability, and accuracy.

Solution of large complex problems in computational electromagnetics using higher-order basis in MoM with out-of-core solvers

In a recent invited paper in the IEEE Antennas and Propagation Magazine, some of the challenging problems in computational electromagnetics were presented. One of the objectives of this note is to simply point out that challenging to one may be simple to another. This is demonstrated through an example cited in that article. The example chosen is a Vivaldi antenna array. What we discuss here also applies to the other examples presented in that article, but we have chosen the Vivaldi antenna array to help us make our point. It is shown in this short article that a higher-order basis using a surface integral equation a la a PMCHWT (Poggio-Miller-Chu-Harrington-Wu-Tsai) method-of-moments formulation may still be the best weapon that one have in today's arsenal to deal with challenging complex electromagnetic analysis problems. Here, we have used the commercially available code WIPL-D to carry out all the computations using laptop/desktop systems. The second objective of this paper is to present an out-of-core solver. The goal is to demonstrate that an out-of-core 32-bit-system-based solver can be as efficient as a 64-bit in-core solver. This is quite contrary to the popular belief that an out-of-core solver is generally much slower than an in-core solver. This can be significant, as the difference in the cost of a 32-bit system can be 1/30 of a 64-bit system of similar capabilities using current computer architectures. For the 32-bit system, we consider a Pentium 4 system, whereas for the 64-bit system, we consider an Itanium 2 system for comparison. The out-of-core solver can go beyond the 2 GB limitation for a 32-bit system and can be run on ordinary laptop/desktop; hence, we can simultaneously have a much lower hardware investment while better performance for a sophisticated and powerful electromagnetic solver. The system resources and the CPU times are also outlined.

BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation

Current computer architecture research relies heavily on architectural simulation to obtain insight into the cycle-level behavior of modern microarchitectures. Unfortunately, such architectural simulations are extremely time-consuming. Sampling is an often-used technique to reduce the total simulation time. This is achieved by selecting a limited number of samples from a complete benchmark execution. One important issue with sampling, however, is the unknown hardware state at the beginning of each sample. Several approaches have been proposed to address this problem by warming up the hardware state before each sample. This paper presents the boundary line reuse latency (BLRL) which is an accurate and efficient warmup strategy. BLRL considers reuse latencies (between memory references to the same memory location) that cross the boundary line between the pre-sample and the sample to compute the warmup that is required for each sample. This guarantees a nearly perfect warmup state at the beginning of a sample. Our experimental results obtained using detailed processor simulation of SPEC CPU2000 benchmarks show that BLRL significantly outperforms the previously proposed memory reference reuse latency (MRRL) warmup strategy. BLRL achieves a warmup that is only half the warmup for MRRL on average for the same level of accuracy.

Implementation, analysis and performance evaluation of the IRP replacement policy

As the processor speeds have improved significantly over the years, memory access penalties have become a major issue. The continuously growing gap between the processor and memory performance is making cache misses more and more expensive. In this paper, we suggest that the most common techniques currently implemented, such as least recently used (LRU) and most frequently used (LFU), are inadequate for current computer architectures as they do not complement each other and in many cases lead to the choice of the wrong line to replace. We propose the use of a more improved cache replacement policy technique in order to reduce the number of cache misses and optimise cache performance. Our solution, the improved replacement policy (IRP) merges the positive features in some of the most common policies and eliminates some of their prevalent drawbacks. IRP also employs the concept of spatial locality and therefore efficiently expels only blocks which are not likely to be accessed again. Finally, the IRP performance is compared to LRU and LFU methods.

Parallel Computing in Optimization.

Parallel Computing in Optimization.

An Object-Oriented Framework for Loop Parallelization

Generation of efficient parallel code is a major goal of a well-designed and developed parallelizing compiler. Another important goal is portability of both compiler system and the resulting output source codes. The various choices of current and future parallel computer architectures as well as the cost of developing a parallelizing compiler make portability a very important design goal. Since the design of parallelizing compilers is considerably move complex than designing conventional compilers, it is very important to achieve both efficiency and portability. To meet this dual goal, we have investigated the application of object oriented design to parallelizing compilers. Our parallelizing compiler design is based on abstractions of intermediate representations of loops and their class definitions. In this paper, we address the problem of loop parallelization and propose a framework where the loop parallelization process is divided into three phases and the optimization of loops is performed via a cyclic application of these three phases. The class of each phase is hierarchically derived from intermediate representations of loops. This facilitates the portability of the resulting parallelizing compilers. Furthermore, one of the phases uses a reservation table of hardware resources in order to obtain optimized parallel programs for given hardware resources. The validation of the proposed framework is given through the application of the object oriented design on an example program which is then parallelized efficiently.

Is your computing environment secure?

In an open distributed system, resources must be shared among various users. Security is one of the major issues in designing such a system. When a computer system is connected to a network, it is very important to ensure that the computer has the ability to manage its local resources securely. In this position paper, we will demonstrate that current computer architectures do give malicious users ways to penetrate computer systems and hence access the system or other user's secrets which are supposed to be well protected. We also propose some possible solutions to counterattack such security threats either at hardware or software level. The impacts of our countermeasures to system hardware and software are also discussed.

Time-sequenced DMA for multimedia computers

Current computer architectures are well suited to the transfer of large amounts of data where latency is not important, and to transfering small amounts of data where latency is important. However, when latency is important and the quantity of data is large, today's computers do not perform so well. In this paper I describe a variety of scatter-gather DMA in which large amounts of data can be transfered with low latency through a computer system by using synchronised clocks in the transmitting and receiving devices.

Computer System Architecture Concepts for Future Combat Systems

ABSTRACTThis paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat.Changes to the current Aegis computer architecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computer architecture to a general architecture for the future.The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor‐based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi‐warfare tactical picture supporting the future combatant command staff.Automatic fault detection and reconfigurability in the current Aegis architecture are expanded in the proposed computer systems architecture concept. The fault detection/reconfigurability scheme of the future architecture will play a key role supporting the continuous availability of the battle force capable combat system for countering the threat of the 21st century.

ASP: a cost-effective parallel microcomputer

The author presents ASP architecture, which offers cost-effective support of a wide range of numerical and nonnumerical computing applications, using state-of-the-art microelectronic technology to achieve processor packing densities that are more usually associated with memory components, ASP is designed to benefit from the inevitable VLSI-to-ULSI-to-WSI (very large, ultra large, and wafer-scale integration) technological trend, with a fully integrated, simply scalable, and defect/fault-tolerant processor interconnection strategy. The author discusses the architectural philosophy, structural organization, operational principles, and VLSI/ULSI/WSI implementation of ASP and indicates its cost-performance potential. ASP microcomputers have the potential to achieve cost-performance targets in the range of 100 to 1000 MOPS (million operations per second) per $1000. This gives ASPs an advantage of two to three orders of magnitude over current parallel computer architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>