Crystalline Ge Layers Research Articles

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects.By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors.In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers.A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistorsFully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices.3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type.3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.

Fabrication of an atomically smooth Ge(111) surface by Au-induced crystallization at 170 °C

Crystalline Ge layer fabricated via layer-exchange metal-induced crystallization is a promising candidate as a seed layer for the epitaxial growth of III–V semiconductor thin films for multijunction solar cells. However, small crystalline islands that grow on top of the crystalline Ge layer are a problem, which roughens the surface and hinders subsequent epitaxial growth. Considering the effect of heating rate on the Au-induced crystallization behavior of Ge, it is found that the temperature required for the island growth in the top Ge layer was higher than that for the bottom layer. By carefully choosing the annealing conditions, the growth of the top Ge layer can be avoided resulting in an atomically smooth Ge(111) surface.

Unprecedented severe atomic redistribution in germanium induced by MeV self-irradiation

We present a pronounced unprecedented surface modification of a crystalline Ge layer under ion irradiation with a Ge ion beam at the energy of 2.5 MeV. Samples were covered by a thin SiN-protection layer to protect from sputtering and surface redeposition phenomena. Under the irradiation conditions, the Ge layer did not become porous as observed for other projectiles and lower energies but develops into a severely uneven morphology with characteristic length scales of several hundred nanometers. The observed roughness monotonically increases with the irradiation doses. We show that this phenomenon is caused neither by the surface erosion effect nor by a non-uniform volumetric expansion. Rather, atomic redistribution in the bulk of the material is the major drive for the uneven surface. Furthermore, the deformation of the Ge layer likely occurs to the largest extent after irradiation, as indicated by the very flat interface around the end-of-range region. The observed morphology modification is discussed based on irradiation-induced plastic flow, coupled with a larger contribution of the electronic component in the ion–solid interactions.

Fabrication of Germanium-on-insulator in a Ge wafer with a crystalline Ge top layer and buried GeO2 layer by oxygen ion implantation

The paper reports fabrication of Germanium-on-Insulator (GeOI) wafer by Oxygen ion implantation of an undoped Ge wafer of orientation (100). O+ ions (energy 200 keV) were implanted to a fluence of 1.9 × 1018 ions-cm−2 and the implanted wafer was subjected to Rapid Thermal Annealing. The resulting wafer has a top crystalline Ge layer of ~ 220 nm thickness and resistivity ≈32 Ohm-cm and a buried Oxide layer (BOX) of crystalline GeO2 (thickness ≈0.62 μm). The crystalline GeO2 layer has hexagonal crystal structure with lattice constants close to the standard values. Raman Spectroscopy and cross-sectional electron microscopy established that the top Ge layer was recrystallized during annealing with a residual tensile strain of around +0.4% and an estimated dislocation density of 2.7 × 107cm−2. The crystallinity and electrical characteristics of the top layer and the quality of the BOX layer are such that it can be utilized for device fabrication.

(Invited) High Performance UTB GeOI n and pMOSFETs Featuring HEtero-Layer-Lift-Off (HELLO) Technology

Introduction Ultrathin body (UTB) Ge-on-insulator (GeOI) is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power CMOS. However, severe carrier mobility degradation has been reported in commercially available Smart-CutTM GeOI substrates with body thickness (T body) less than 20 nm [1, 2]. Unstable Ge/buried oxide (BOX) interfaces, poor Ge crystallinity and Ge thickness fluctuation are main obstacles in conventional UTB GeOI structures. Therefore, more sophisticated fabrication methods are strongly required. In this work, a novel Ge layer transfer technology called HEtero-Layer-Lift-Off (HELLO) [3] utilizing SiGe etch stop layer and Si passivation layer in the donor structure has been developed for precise control of T body and back interfacial quality in UTB GeOI. Enhancement of carrier mobility in both UTB GeOI n and pMOSFETs has been demonstrated, showing high potential of UTB GeOI by HELLO technology [4, 5]. HELLO technology The schematic flows of HELLO technology for fabricating GeOI substrates is shown in Fig. 1. As a donor structure, Ge channel (20 nm)/Si0.3Ge0.7 etch stop layer (6.5 nm)/Ge buffer layer (500 nm)/AlAs/GaAs hetero-structures were grown by low-pressure CVD. To improve back interfacial quality, plasma treatment or 0.5-nm-thick Si passivation on top of Ge layer prior to ALD-Al2O3 deposition were carried out for GeOI n or pMOSFETs, respectively. Then, the direct bonding to SiO2/Si host substrate was performed in press machine under vacuum at 200 °C. Note that the direct bonding was performed at interface of Al2O3/SiO2 to prevent the damage for Ge channel layer. To release GaAs substrate, the AlAs layer was etched selectively and laterally in HCl solution at room temperature. Then, Ge buffer layer and Si0.3Ge0.7 etch stop layer were etched, sequentially. This HELLO technology was performed at low temperature to avoid thermal stress, leading to high quality GeOI structure. The detailed fabrication method for GeOI MOSFETs can be found elsewhere [4]. GeOI n and pMOSFETs Figures 2 show the I D-V G transfer chcaracteristics of UTB GeOI n and pMOSFETs fabricated with HELLO technology with T body of 3 and 4 nm, respectively. Comparable device performance has been achieved and a high I on-I off ratio of 105 has been obtained in both devices. The TEM image of ultrathin GeOI channel (3 nm) in MOSFETs fabricated through HELLO technology is also shown in the inset. Single crystalline Ge layer with precise channel thickness control down to 3 nm was achieved. Positive V th shift was observed in GeOI pMOSFETs as compared with that of nMOSFETs, which can be attributed to carrier confinement at Si-passivated GeOI back interface owing to Ge/Si valence band offset. Figures 3 show the benchmarks of T body dependence of effective (a) electron and (b) hole mobility at N S of 2×1012 cm-2. The mobility of reported GeOI [1, 2] and SOI devices [6] are also plotted for comparison. Severe mobility degradation with scaling T body was found for both n and pMOSFETs as fabricated with conventional GeOI substrates. Nevertheless, it was confirmed the effective electron mobility in HELLO fabricated GeOI significantly increased with scaling T body below 10 nm. This unique phenomenon may be attributed to the modulation of Ge conduction band structure [4]. On the other hand, GeOI pMOSFETs attained much higher mobility of about 150 cm2/Vs in UTB regime. The trend of mobility degradation with scaling T body was also suppressed for the devices fabricated with HELLO technology, presenting the clear benefit of reducing thickness fluctuation and Si-passivated back interface. Thanks to HELLO technology, for the first time, GeOI n and pMOSFETs both outperformed their SOI counterparts in UTB regime. Conclusion High quality GeOI substrates have been successfully fabricated through HELLO technology. Both electron and hole mobility in GeOI devices outperformed their SOI counterparts in UTB regime, indicating that UTB-GeOI structure is very promising for future Ge CMOS applications. Acknowledgement The authors would like to thank the support from Sumitomo Chemical Co., Ltd. and Hitachi Kokusai Electric Inc. for Ge layer transfer technology and AIST-NPF for device fabrication.

Low-temperature (330 °C) crystallization and dopant activation of Ge thin films via AgSb-induced layer exchange: Operation of an n-channel polycrystalline Ge thin-film transistor

Ge thin films have been prepared by layer-exchange metal-induced crystallization using AgSb alloy as a catalyst. Not only the crystallization of Ge, but also the incorporation of Sb atoms into the crystalline Ge layer and their activation have been realized during the process at a temperature as low as 330 °C. Thin-film transistors have been fabricated using the Ge thin films as channel layers and the operation of an n-channel transistor with an on/off ratio of over 300 has been demonstrated.

Implantation and Activation of Phosphorus in Amorphous and Crystalline Germanium Layers

We have investigated phosphorus implantation and activation in amorphous and crystalline Ge layers, deposited on Si substrates. The structure of the Ge layer has only limited influence on the dopant profile and diffusion after annealing. Surprisingly, crystalline Ge layers show better electrical results after implantation and dopant activation. For the amorphous layer, the solid phase epitaxy process is influenced in the neighborhood of P, leading to point defects, which inhibit electrical activation. This result implies that when a crystalline Ge layer is amorphized during implantation of high doses, the dopant activation can be significantly reduced. Reduced temperature ramping improves activation of P in amorphous Ge layers.

High-Quality Single Crystalline Ge(111) Growth on Si(111) Substrates by Solid Phase Epitaxy

Heterogeneous integration of crystalline Ge layers on cleaned and H-terminated Si(111) substrates are demonstrated by employing a combination of e-beam evaporation and solid phase epitaxy techniques. High-quality single crystalline Ge(111) layers on Si(111) substrates with a smooth Ge surface and an abrupt interface between Ge and Si are obtained. An XRD rocking curve scan of the Ge(111) diffraction peak shows a FWHM of only 260 arcsec for a 50-nm-thick Ge layer annealed at 600°C with a ramp-up rate of 20°C/s and a holding time of 1 min. The AFM images exhibit that the rms surface roughness of all the crystalline Ge layers are less than 2.1 nm.

Atomically smooth and single crystalline Ge(111)/cubic-Pr2O3(111)/Si(111) heterostructures: Structural and chemical composition study

Engineered wafer systems are an important materials science approach to achieve the global integration of single crystalline Ge layers on the Si platform. Here, we report the formation of single crystalline, fully relaxed Ge(111) films by molecular beam epitaxial overgrowth of cubic Pr oxide buffers on Si(111) substrates. Reflection high-energy electron diffraction, scanning electron microscopy, and x-ray reflectivity show that the Ge epilayer is closed, flat, and has a sharp interface with the underlying oxide template. Synchrotron radiation grazing incidence x-ray diffraction and transmission electron microscopy reveal the type-A/B/A epitaxial relationship of the Ge(111)/cubic Pr2O3(111)/Si(111) heterostructure, a result also corroborated by theoretical ab initio structure calculations. Secondary ion mass spectroscopy confirms the absence of Pr and Si impurities in the Ge(111) epilayer, even after an annealing at 825 °C.

High performance germanium MOSFETs

Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride (GeO x N y ) and high-permittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric constant, most high mobility materials suffer from large band-to-band tunneling (BTBT) leakage currents and worse short channel effects. We present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel mobility, making them suitable for scaling into the sub-15 nm regime. Through full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying strained-Ge or SiGe thickness, Si cap thickness and Ge percentage were fabricated on bulk Si and SOI substrates. The ultra-thin (∼2 nm) strained-Ge channel heterostructure MOSFETs exhibited >4× mobility enhancements over bulk Si devices and >10× BTBT reduction over surface channel strained SiGe devices.

Germanium MOSFETs for Nanoelectronics

Ge is a promising channel material for nanoscale MOSFETs due to its high mobility, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully-relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride and high-k metal oxides of Al, Zr and Hf. High mobility p-MOSFETs have been demonstrated in bulk Ge with these gate dielectrics and metal gates. However, due to its smaller bandgap Ge suffers from large leakage currents. We present novel, Si and Ge based heterostructure MOSFETs, which significantly reduce the leakage while retaining high mobility, making them suitable for scaling into the sub-20nm regime.

Low-temperature non-metal-induced crystallization of germanium for fabrication of thin-film transistors

Device-quality poly-Ge layers were grown at temperatures as low as 200 °C by successive hydrogenation and annealing steps, with no need to any metal incorporation. Hydrogenation is performed in a PECVD apparatus with 150 W RF hydrogen plasma and annealing is carried out in the same system in N 2 ambient. As a result, grains of the order of 100 nm are formed in the Ge layer. It has been observed that hydrogenation at high temperatures may be destructive to the Ge layer. Successive hydrogenation and annealing at respective temperatures of 150 and 200 °C would result in a device-quality poly crystalline Ge layer which has been employed for fabrication of depletion-mode thin-film transistors. These TFTs show a field-effect mobility of 80 cm 2/Vs for holes and an ON/OFF ratio of more than 10 3, indicating the feasibility of this technique for applications in large-area electronics.