Crystal Wafers Research Articles

Experimental study regarding the surface roughness of circular crystal wafers sliced by a multi-wire saw with reciprocating and rocking functions

Experimental study regarding the surface roughness of circular crystal wafers sliced by a multi-wire saw with reciprocating and rocking functions

Impact of Binder Thin-Films on Surface Chemistry of Silicon Anodes in Lithium-Ion Batteries

The effect of polymer binder on the nature and location of solid-electrolyte interphase (SEI) formation on Si active material was investigated. Thin layers of polymeric binder (polyvinylidene fluoride and sodium carboxymethyl cellulose) were spin-coated onto polished single crystal Si wafers. The samples were cycled against a Li counter/reference electrode under various electrochemical conditions in a coin cell configuration. The electrolyte was 1 M of LiPF6 in 1:1:1 wt% EC:DEC:DMC. After cycling, the samples were extracted from the coin cell under inert conditions and X-ray photoelectron spectroscopy (XPS) was performed. Electron microscopy and atomic force microscopy indicate that the binder films are smooth and continuous across the wafer surface, and no impact on the electrochemical behavior was observed. However, notable differences were detected using XPS, which revealed both difference in SEI composition and location relative to the binder-electrolyte and binder-substrate interfaces. These observations and insights will be useful in cell designs, binder selection, and reliability estimates because the location of SEI formation may influence cyclic performance of electrodes.

Space-Confined Growth for Thickness-Controlled Cs3Bi2I9 Perovskite Single Crystal Wafers for X-Ray Detectors.

The Cs3Bi2I9 single crystal, as an all-inorganic non-lead perovskite, offers advantages such as stability and environmental friendliness. Its superior photoelectric properties, attributed to the absence of grain boundary influence, make it an outstanding X-ray detection material compared to polycrystals. In addition to material properties, X-ray detector performance is affected by the thickness of the absorption layer. Addressing this, a space-confined method is proposed. The temperature field is determined through finite element simulation, effectively guiding the design of the space-confined method. Through this innovative method, a series of thickness-controlled perovskite single crystal wafers (PSCWs) are successfully prepared. Corresponding X-ray detectors are then prepared, and the impact of single crystal thickness on device performance is investigated. With an increase in single crystal thickness, a rise followed by a decline in device sensitivity is observed, reaching an optimal value at 0.7mm thickness at 40V mm-1 with a device performance of 11313.6µCGy-1cm-2. This space-confined method enables the direct growth of high-quality perovskite single crystals with specified thickness, eliminating the need for slicing or etching.

Crack Catcher AI – Enabling smart fracture mechanics approaches for damage control of thin silicon cells or wafers

Silicon has been one among a few key technologically important materials especially in our modern world. Silicon, especially in its current most useful forms (thin layers), is a brittle material by nature. Thin silicon cells crack easily during manufacturing assembly. Every crack is a defect in any PV manufacturing lines, and if let to grow/propagate it will lead to reliability and quality issues with time. Nevertheless, the global silicon solar PV industry is aggressively reducing the cost of solar PV systems through cutting down the thickness of silicon solar cells. Cell cracks immediately lower PV module efficiency and can lead to premature aging of the entire module. The “Crack Catcher AI” was our research joint collaboration's entry in the Department of Energy (DOE)'s American-Made Solar Innovation competition in 2022 (Round 6) which later was selected as the national semifinalists and won an award announced by DOE in December 2022. It uses smart stress sensing and smart fracture prediction approaches utilizing fundamental fracture mechanics and big data analytics to reduce crack defects and enhance long-term durability/reliability of PV products/devices. Smart Stress Sensing uses a novel laser-based curvature methodology for fast in-line stress metrology in manufacturing lines. Smart Fracture Prediction uses Artificial Intelligence (AI) for defect control metrology and yield enhancement in PV production lines. It is based on monocrystalline silicon used in solar PV industries, but all scientific principles utilized and technological innovations developed in this article would be applicable as well for single crystal silicon semiconductor wafers.

Linear vs. Non-linear Behaviour in Ion Irradiation Nanostructuring of Nickel and Silicon Surfaces

Spontaneous nanometre-scale quasi-periodic ripple-like structures are formed at the surface of polycrystalline Ni films and Si(111) single crystal wafers by irradiation with a broad Ar+ ion beam at room temperature and studied with Atomic Force Microscopy as a function of fluence. The development of these structures can be reproduced by numerical solution of a continuum equation describing the evolution of surface morphology under ion irradiation, using realistic coefficients derived from material properties. In particular, we demonstrate that differences observed in pattern formation on the two surfaces under the conditions studied, such as wavelength stability and exponential growth of interface width for the Ni surfaces compared with wavelength coarsening and interface width saturation on Si(111), can be understood in terms of a cross-over between linear and non-linear behaviours.

Mechanism of friction-induced chemical reaction high-efficient polishing single crystal 4H-SiC wafer using pure iron

This paper proposes a novel method for friction-induced chemical reaction machining of single-crystal 4H-SiC wafers using pure iron. Material Removal Rate (MRR) and surface quality of single-crystal 4H-SiC were studied, and the results demonstrate that both high surface quality and high MRR (Ra: 2.2 nm, MRR: 375 nm/min) were obtained. The mechanism of material removal during friction was investigated by examining the critical roles of friction speed. Solid-state chemical reactions between metal and SiC surfaces can be induced by friction, and the subsequent removal of reactants, resulting in a near-damage-free machined surface. A removal mechanism model of friction was established, which reveals that both the rates of solid-state reaction and reactant removal significantly impact the final removal rate of friction.

Indentation fracture of 4H-SiC single crystal

Understanding the deformation and fracture behavior of single crystal silicon carbide (SiC) under a single particle is of scientific and practical importance for the micromachining of single crystal SiC. In this work, we investigate the indentation fracture of a 4H-SiC single crystal wafer with the indentation direction perpendicular to (0001) plane, using Berkovich, Vickers, and Knoop indenters. All the indentations create radial cracks for the normal loads used in this work. Both the Vickers and Knoop hardness tests produce lateral cracks. The fracture toughness calculated from the Vickers hardness tests is smaller than the ones calculated from the Knoop hardness tests and the Berkovich indentations under large indentation loads. The fracture toughness of 4H-SiC single crystal decreases with the increase of the indentation load under small indentation loads for the Berkovich indentations, revealing the phenomenon of surface hardening. The surface energy calculated from the radial cracks is comparable to the results reported in the literature. We establish an analytical expression of the total energy dissipation of a single indentation cycle, including the contribution of indentation-induced cracking, which offers an approach to calculate the ratio of the energy dissipation due to cracking to the energy dissipation due to plastic deformation and determine the dominant deformation process controlling the indentation deformation. The analysis of the energy dissipation for the indentations of the 4H-SiC single crystal by the Berkovich indenter reveals that the energy dissipation from the indentation-induced cracking is significantly larger than (more than eight times) that from plastic deformation for the indentation loads larger than 75 mN.

Anisotropic carrier dynamics and laser-fabricated luminescent patterns on oriented single-crystal perovskite wafers

Perovskite materials and their applications in optoelectronics have attracted intensive attentions in recent years. However, in-depth understanding about their anisotropic behavior in ultrafast carrier dynamics is still lacking. Here we explore the ultrafast dynamical evolution of photo-excited carriers and photoluminescence based on differently-oriented MAPbBr3 wafers. The distinct in-plane polarization of carrier relaxation dynamics of the (100), (110) and (111) wafers and their out-of-plane anisotropy in a picosecond time scale were found by femtosecond time- and polarization-resolved transient transmission measurements, indicating the relaxation process dominated by optical/acoustic phonon interaction is related to photoinduced transient structure rearrangements. Femtosecond laser two-photon fabricated patterns exhibit three orders of magnitude enhancement of emission due to the formation of tentacle-like microstructures. Such a ultrafast dynamic study carried on differently-oriented crystal wafers is believed to provide a deep insight about the photophysical process of perovskites and to be helpful for developing polarization-sensitive and ultrafast-response optoelectronic devices.

Analysis Of Silicon Crystal Materials: Meeting Growing Demands Across Industries

The demand for silicon crystal materials is poised for continued growth across diverse sectors in the upcoming years. In the realm of computers and communication, silicon single crystal wafers and chips are in high demand, fueled by the increasing adoption of communication equipment and the essential requirement for memory and control chips in information processing systems. Beyond the electronics domain, silicon crystals find applications in various industries, including environmental protection, new energy, and construction. In the field of environmental protection, silicon crystals play a vital role in denitrification and dust removal devices. In the new energy sector, they contribute to solar photovoltaic power generation systems and geothermal power generation systems. In construction, silicon crystals find their place in the production of building glass and semiconductor building materials. As China's economy continues to evolve and environmental concerns gain prominence, the demand for semiconductor materials, including silicon crystal materials, is anticipated to rise. This underscores a bright market outlook for silicon crystal materials in the foreseeable future.

Li3Na7B4P6O26: a new ultraviolet transparent congruently melting non-linear optical crystal.

The exploration of nonlinear optical crystals with ultraviolet (UV) transparent ranges and easy-to-grow large-size crystals is one of the current research interests. Herein, by combining borate and phosphate groups, a novel congruently melting alkali-mixed metal borophosphate, Li3Na7B4P6O26 (LNBPO) with UV transparency was successfully designed and synthesized using a high-temperature flux method. LNBPO crystallizes in the non-centrosymmetric (NCS) and polar orthorhombic space group Pca21 (no. 29), showcasing interesting (B2P3O13)∞ chains along the c axis. Notably, LNBPO has a moderate second harmonic generation (SHG) response (∼0.38 × KDP) and displays a wide transmission ranging from 0.22 to 3.68 μm, as measured by a [001]-oriented crystal wafer. Furthermore, a high-quality single crystal of LNBPO with sizes up to 14 × 14 × 12 mm3 was grown using the top-seeded solution growth method. The refractive indices of LNBPO were determined by applying the minimum deviation angle method. These results show that LNBPO possesses a phase-matching wavelength as short as 483 nm, indicating its potential as a new UV NLO crystal.

(Invited) Challenges in Fabricating and Scaling up Silicon Carbide Wafers and Devices

Silicon Carbide is rapidly growing in the power electronics industry. This is fueled to a great degree by the adoption of electric cars and power electronics needed both inside the vehicle and to support the charging infrastructure. This attention from automotive industry comes with a clear spotlight on the cost, quality, and efficiency of SiC power devices. This in turn results in intense pressure and scrutiny to improve yields and reduce defects in every part of the manufacturing chain. There is a wide release and proliferation of Diode and MOSFET devices from various companies in the marketplace. Several companies are investing billions of dollars in capacity expansions driving exponential growth of wafers and devices.In this review, we will discuss the steps and processes of fabricating a SiC wafer including crystal growth, wafering, epitaxy and device fabrication. The process challenges associated with the steps unique to SiC will be highlighted with a perspective on scaling up volumes and the transition to 200mm wafers. New innovations at some of the steps are enabling higher efficiency and output. The impact of these innovations will be presented. In addition, defects at each step of the process will be reviewed along with how they interact with the following steps [1]. Finally, the effect of various processes and defects on devices and reliability will be presented [2,3].

Electrochemical etching strategy for shaping monolithic 3D structures from 4H-SiC wafers

Silicon Carbide (SiC) is an outstanding material, not only for electronic applications, but also for projected functionalities in the realm of spin-based quantum technologies, nano-mechanical resonators and photonics-on-a-chip. For shaping 3D structures out of SiC wafers, predominantly dry-etching techniques are used. SiC is nearly inert with respect to wet etching, occasionally photoelectrochemical etching strategies have been applied. Here, we propose an electrochemical etching strategy that solely relies on defining etchable volumina by implantation of p-dopants. Together with the inertness of the n-doped regions, very sharp etching contrasts can be achieved. We present devices as different as monolithic cantilevers, disk-shaped optical resonators and membranes etched out of a single crystal wafer. The high quality of the resulting surfaces can even be enhanced by thermal treatment, with shape-stable devices up to and even beyond 1550°C. The versatility of our approach paves the way for new functionalities on SiC as high-performance multi-functional wafer platform.

Advanced approach of bulk (111) 3C-SiC epitaxial growth

3C-SiC films grown on (111) Si substrates exhibit poor crystal quality and experience wafer cracks and bowing preventing access to bulk growth. This work reports innovative Chemical Vapor Deposition (CVD) growth methodology on 4 in. Si substrates which allowed the growth of 230 mm thick layer of (111) 3C-SiC through the melting of the Si substrate in the CVD chamber and the adoption of the resulting free standing 3C-SiC for the growth of bulk (111) 3C-SiC layer under high N fluxes. From the molten KOH etching and subsequent SEM investigation it has been ascertained that with a N2 flux of 1600 sccm there is a significant reduction in the concentration of stacking faults (SFs) from (7.16 ± 0.04) × 103 cm−1 to (0.4 ± 0.3) × 103 cm−1. This reduction is consistent with the cross section m-PL response displaying steep and uniform increase in the intensity of the band-edge signal a factor 10 higher on the surface with respect to the equal (100) 3C-SiC grown thickness. Furthermore, the emission attributed to point defects is considerably lower in (111) 3C-SiC. From Scanning Transmission Electron Microscopy (STEM) investigation it appears evident how the typical mechanism valid in (100) growths consisting in the mutual closure of SFs coming from opposing {111} planes that give rise to Lomer and l-shaped dislocations is replaced by a different panorama of evolution. Indeed, it is shown how the SFs shred but do not interrupt each other during growth. Furthermore, dropping in the number of atomic planes composing SFs layers appears to be a key phenomenon leading to both the shrinkage of the number of SF atomic layers as well as to the SF self-closure. High Angle Annular Dark Field-Scanning Transmission Electron Microscopy (HAADF-STEM) attested how the crystal tends to smooth out the lattice mismatch until the SF is suppressed. Because of the foregoing, the mechanisms of evolution of the defects in (111) 3C-SiC revealed in this study, demonstrates how the growth parameters must be matched with the kinetics of the defects in order to endorse (111) 3C-SiC adoption in high performing devices.

Building Block-Inspired Hybrid Perovskite Derivatives for Ferroelectric Channel Layers with Gate-Tunable Memory Behavior.

Ferroelectric photovoltaics driven by spontaneous polarization (Ps ) holds a promise for creating the next-generation optoelectronics, spintronics and non-volatile memories. However, photoactive ferroelectrics are quite scarce in single homogeneous phase, owing to the severe Ps fatigue caused by leakage current of photoexcited carriers. Here, through combining inorganic and organic components as building blocks, we constructed a series of ferroelectric semiconductors of 2D hybrid perovskites, (HA)2 (MA)n-1 Pbn Br3n+1 (n=1-5; HA=hexylamine and MA=methylamine). It is intriguing that their Curie temperatures are greatly enhanced by reducing the thickness of inorganic frameworks from MAPbBr3 (n=∞, Tc =239 K) to n=2 (Tc =310 K, ΔT=71 K). Especially, on account of the coupling of room-temperature ferroelectricity (Ps ≈1.5 μC/cm2 ) and photoconductivity, n=3 crystal wafer was integrated as channel field effect transistor that shows excellent a large short-circuit photocurrent ≈19.74 μA/cm2 . Such giant photocurrents can be modulated through manipulating gate voltage in a wide range (±60 V), exhibiting gate-tunable memory behaviors of three current states ("-1/0/1" states). We believe that this work sheds light on further exploration of ferroelectric materials toward new non-volatile memory devices.

Building Block‐Inspired Hybrid Perovskite Derivatives for Ferroelectric Channel Layers with Gate‐Tunable Memory Behavior

AbstractFerroelectric photovoltaics driven by spontaneous polarization (Ps) holds a promise for creating the next‐generation optoelectronics, spintronics and non‐volatile memories. However, photoactive ferroelectrics are quite scarce in single homogeneous phase, owing to the severe Ps fatigue caused by leakage current of photoexcited carriers. Here, through combining inorganic and organic components as building blocks, we constructed a series of ferroelectric semiconductors of 2D hybrid perovskites, (HA)2(MA)n‐1PbnBr3n+1 (n=1–5; HA=hexylamine and MA=methylamine). It is intriguing that their Curie temperatures are greatly enhanced by reducing the thickness of inorganic frameworks from MAPbBr3 (n=∞, Tc=239 K) to n=2 (Tc=310 K, ΔT=71 K). Especially, on account of the coupling of room‐temperature ferroelectricity (Ps≈1.5 μC/cm2) and photoconductivity, n=3 crystal wafer was integrated as channel field effect transistor that shows excellent a large short‐circuit photocurrent ≈19.74 μA/cm2. Such giant photocurrents can be modulated through manipulating gate voltage in a wide range (±60 V), exhibiting gate‐tunable memory behaviors of three current states (“‐1/0/1” states). We believe that this work sheds light on further exploration of ferroelectric materials toward new non‐volatile memory devices.

Cutting force modeling and control of single crystal silicon using wire saw velocity reciprocation

Single crystal silicon wafers are often used as substrate material for integrated circuits. Often the wafer is cut by a wire with fixed abrasive diamond owning to a narrow kerf and a low cutting force. The cutting force changes during the process as the direction of wire movement continuously reverses (i.e., reciprocates), which may cause the wire saw to break, the wafer to collapse, and the wafer surface roughness to decrease even if the wire saw tension and the contact length between the wire and the wafer are fixed. In this work, a cutting force model including both normal and tangential forces was established to determine the relationship between the normal and tangential forces and the commanded wire speed. Separate controllers were developed to regulate both the normal force and the tangential force by adjusting the wire velocity. Experimental studies were conducted for wire saw processing of single crystal silicon wafers. Compared with a process using constant wire velocity, regulating the normal force can significantly reduce the processing time and the wafer surface roughness. The average improvements in processing time and wafer surface roughness are approximately 11% and 56%, respectively, when using normal force control, and approximately 29% and 30%, respectively, when using tangential force control. The results show that the normal and tangential forces can be well regulated during the machining process. In addition, the wafer surface roughness and machining time were lower in both experiments where the forces were regulated than in the experiment where a constant wire velocity was used. This paper demonstrates that the novel concept of regulating process forces in wire saw machining by adjusting the wire velocity can be used to optimize the cutting process of single crystal silicon, making the process more productive while decreasing the part roughness.

Confirmation of n‐Hexane as an Inert Co‐Solvent in the Production of Functionalized Silicon Nanoparticles from Reactive High‐Energy Ball Milling

AbstractAlkanes such as n‐hexane have been used as co‐solvents in the production of functionalized semiconductor nanoparticles from alkenes and alkynes using Reactive High Energy Ball Milling (RHEBM) under the assumption that they are non‐reactive under typical milling conditions. In this paper, a comparative study with two hydrocarbon solvents of comparable chain length, 1‐hexyne, and n‐hexane, and their milling products using three different commercially available silicon precursors, namely single crystal silicon wafers and polycrystalline particles having a nominal size of 4 µm and 1 mm, is reported. It is found that nanoparticle formation and surface functionalization in all the three silicon systems occurs only with 1‐hexyne; n‐hexane is non‐reactive and does not lead to appreciable functionalized nanoparticle formation under the conditions studied. Nanoparticles (where formed) and microparticle byproducts of appropriate samples are characterized by Transmission electronic microscope (TEM), Fourier transform infrared (FTIR), Photoluminiscence spectroscopy (PL), Nuclear magnetic resonance 1H/13C NMR, and thermogravimetry TGA to separately confirm nanoparticle formation and surface functionalization.

Growth and characterization of holmium-doped yttrium iron garnet single crystal

Yttrium iron garnet (YIG) crystals are the primary candidate for non-reciprocal device. With the miniaturization and integration of optical communication devices, the modified YIG crystals with excellent comprehensive performances are highly desired. To explore the possible mechanism of rare earth ions doping on Faraday effect, holmium oxide-doped YIG (Ho0.6Y2.4Fe5O12, abbreviated as HYIG) crystal was grown by molten salt method. Its structure, optical transparency, magnetic, magneto-optical properties and oxygen atmosphere annealing processes were first investigated systematically. The HYIG crystal wafers annealed at 800 °C for 2 h can achieve the large Faraday rotation angle (186 deg/cm at 1310 nm; 148 deg/cm at 1550 nm) and good optical transparency (73.64 % at 1310 nm; 74.83 % at 1550 nm), which is increased by approximately 10 % compared to the unannealed sample. This result may provide a new insight into the investigation of rare earth doped YIG crystals and their atmosphere annealing processes.

Study on surface characteristics of as-sawn sapphire crystal wafer considering diamond saw wire wear

Sapphire crystal is widely used as Light Emitting Diode (LED) substrate and window materials for electronic devices. During the sawing process of sapphire crystal, the wear of saw wire leads to different sawing performance. In this paper, the abrasives wear state, the diameter change and wear rate of the saw wire, the change of surface morphology and surface roughness (SR) of as-sawn sapphire crystal wafer during the whole service cycle of saw wire under typical sawing parameters were analyzed, and the stable service period of diamond saw wire was determined. Further, sawing experiments were conducted during the stable service period of diamond saw wire, and the effects of sawing parameters within the industrial production on the as-sawn sapphire crystal wafers surface characteristics were studied. The results show that within range of sawing parameters adopted in this paper, the abrasives mainly remove the material in a brittle mode, and the SR of the as-sawn wafers decreases as the saw wire speed increases (from 1000 m/min to 1600 m/min), and the as-sawn wafer surface morphology is improved. As the specimen feed speed increases (from 0.05 mm/min to 0.5 mm/min), the SR increases, and the consistency of the as-sawn wafer surface morphology deteriorates.

Study on subsurface microcrack damage depth of diamond wire as-sawn sapphire crystal wafers

Sapphire crystals are widely used as window materials for infrared emitting devices, high intensity lasers, optical elements and microelectronic substrates due to the excellent material properties. The subsurface microcrack damage produced by diamond wire saw when cutting sapphire crystal is an important indicator of the cutting quality. In this paper, diamond wire sawing experiments were conducted within the industrial production processing parameters to investigate the as-sawn sapphire crystal wafers subsurface microcrack damage depth (SSD), and a numerical calculation model was established to predict the SSD based on the analysis of the scratching stress field of single abrasive. The effects of the saw wire speed and specimen feed speed, saw wire parameters on SSD were predicted. The results show that, within the parameters studied in this paper, the material was removed in brittle mode, increasing the saw wire speed (from 1000 m/min to 1600 m/min) and reducing the specimen feed speed (from 0.5 mm/min to 0.05 mm/min) can reduce the sapphire as-sawn wafers SSD, reduce the size of brittle tear-shape edge breakage, the number and size of brittle pits on the as-sawn wafer surface are reduced and the surface morphology consistency is improved. Increasing the abrasive density and reducing the abrasive size can reduce the SSD. The study results provide a reference for the reasonable matching of sawing process parameters and saw wire parameters in industry.