Cryptographic Modules Research Articles

Countermeasures in CPU for Timing and Power Side Channel Attack

Security chip is the critical component for information security system. Cryptographic modules for various algorithms and random number generation are usually provided inside the security chip. They are essential elements for achieving the confidentiality, integrity, and availability of the entire system. However, sensitive data in security chips are often assigned to other components through CPU operations, and transfers, so CPU security is also an essential part of the security chip. In order to improve the anti-side channel attack capability of CPU, this paper puts forward several countermeasures, including: unified instruction execution time, random switch of idle component, random switch of data bus, and randomization of program execution time. Some of these countermeasures are anti timing attack, some of which are anti power attack. By adopting multiple protection measures in CPU, it not only reduces the information leakage problem when sensitive information passes through the CPU, but also provides a powerful supplement to enhance the security of the other cryptographic components in the chip.

A comparative analysis of VLSI trusted virtual sensors

This paper analyzes three cryptographic modules suitable for digital designs of trusted virtual sensors into integrated circuits, using 90-nm CMOS technology. One of them, based on the keyed-hash message authentication code (HMAC) standard employing a PHOTON-80/20/16 lightweight hash function, ensures integrity and authentication of the virtual measurement. The other two, based on CAESAR (the Competition for Authenticated Encryption: Security, Applicability, and Robustness) third-round candidates AEGIS-128 and ASCON-128, ensure also confidentiality. The cryptographic key required is not stored in the sensor but recovered in a configuration operation mode from non-sensitive data stored in the non-volatile memory of the sensor and from the start-up values of the sensor SRAM acting as a Physical Unclonable Function (PUF), thus ensuring that the sensor is not counterfeit. The start-up values of the SRAM are also employed in the configuration operation mode to generate the seed of the nonces that make sensor outputs different and, hence, resistant to replay attacks. The configuration operation mode is slower if using CAESAR candidates because the cryptographic key and nonce have 128 bits instead of the 60 bits of the key and 32 bits of the nonce in HMAC. Configuration takes 416.8 µ s working at 50 MHz using HMAC and 426.2 µ s using CAESAR candidates. In the other side, the trusted sensing mode is much faster with CAESAR candidates with similar power consumption. Trusted sensing takes 212.62 µ s at 50 MHz using HMAC, 0.72 µ s using ASCON, and 0.42 µ s using AEGIS. AEGIS allows the fastest trusted measurements at the cost of more silicon area, 4.4 times more area than HMAC and 5.4 times more than ASCON. ASCON allows fast measurements with the smallest area occupation. The module implementing ASCON occupies 0.026 mm2 in a 90-nm CMOS technology.

A 0.18-μm CMOS high-data-rate true random bit generator through ΔΣ modulation of chaotic jerk circuit signals.

A full-custom design of chaos-based True Random-Bit Generator (TRBG) implemented on a 0.18-μm CMOS technology is presented with unique composition of three major components, i.e., (i) chaotic jerk oscillator, (ii) ΔΣ modulator, and (iii) simple pre/post-processing. A chaotic jerk oscillator is a deterministic source of randomness that potentially offers robust and highly random chaotic signals and exhibits a distinctive property of smoothly balanced-to-unbalanced alternation of double-scroll attractors. The continuous-time 2nd-order ΔΣ modulator is introduced as a mixed-signal interface in order to increase a resolution of random bit sequences while no extra clock is required. The ΔΣ modulator is constructed mainly by a folded-cascode amplifier with sufficient gain and phase margin of 64 dB and 83°, respectively, and a high-speed comparator with a time constant of 2.7 ns. An uncomplicated structure of shift-registers is realized as a post-processing process. The bit sequence of the proposed TRBG successfully passes all statistical tests of NIST SP800-22 test suite, and the ultimate output bit rate is 50 Mbps. The physical layout of a chip area is 212.8 × 177.11 μm and the DC power dissipation is 1.32mW using a 1.8-V single supply voltage. This paper therefore offers a potential alternative to a fully embedded cryptographic module in ASIC applications.

Towards data storage in cryptographic systems: an efficient hardware architecture based on multivariate scheme for secure storage applications

Secure storage devices are a good example of the Internet of Things (IoTs), which require secure access control mechanisms via using the prominent pubic key cryptographic systems, e.g. RSA, ECC and related systems. However, quantum computer is in a position to attack RSA, ECC and other signature algorithms adopted by many storage devices. Therefore, storage security is facing severe threats. In this paper, an efficient hardware architecture based on multivariate scheme for storage devices is proposed. Multivariate scheme belongs to multivariate public key cryptography (MPKC), which uses affine transformations and central map transformations during cryptographic operations. The advantage of adopting multivariate scheme is that multivariate scheme is immune to quantum computer attack. The efficient hardware architecture is composed of processor module, cryptographic module, storage module, display module, power module, keyboard module, export module and terminal module (off-chip). We implement the hardware architecture on the methodology of TSMC-0.18 μm standard cell CMOS Application Specific Integrated Circuit. The implementation results show that the architecture based on multivariate scheme is very efficient and well suit for storage devices.

FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices

With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficient and secure IoT devices. For example, IoT devices such as radio frequency identification tags and wireless sensor nodes employ AES cryptographic module that are susceptible to differential power analysis (DPA) attacks. With the scaling of technology, leakage power in the cryptographic device increases, which increases their vulnerability to DPA attack. This paper presents a novel FinFET-based secure adiabatic logic (FinSAL), that is energy-efficient and DPA-immune. The proposed adiabatic FinSAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on adiabatic FinSAL are used to implement a positive polarity Reed Muller architecture-based S-box circuit. SPICE simulations at 12.5 MHz show that adiabatic FinSAL (20-nm FinFET technology) S-box circuit saves up to 81% of energy per cycle as compared to the conventional S-box circuit implemented using FinFET (20-nm FinFET technology). Further, the security of adiabatic FinSAL S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the FinSAL S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, the impact of FinSAL on hardware security at different technology nodes of FinFETs (7, 10, 14, and 16 nm) are evaluated. From the simulation results, FinSAL gates at 14-nm FinFET offer superior security with optimum power consumption, therefore is the best candidate to design low-power secure IoT devices.

Nanocircuits for the cryptographic modules

The possibility of introducing non-emitting nanoscales on the basis of quantum cellularautomata has been investigated. It practically neutralizes electromagnetic attacks. The method ofprotection from external interferences and observations of electromagnetic radiation (attacks) isproposed in the work. The power consumption of cryptographic modules has been reduced by five orders.Secure encryption of cryptographic information is provided

A Survey of Timing Channels and Countermeasures

A timing channel is a communication channel that can transfer information to a receiver/decoder by modulating the timing behavior of an entity. Examples of this entity include the interpacket delays of a packet stream, the reordering packets in a packet stream, or the resource access time of a cryptographic module. Advances in the information and coding theory and the availability of high-performance computing systems interconnected by high-speed networks have spurred interest in and development of various types of timing channels. With the emergence of complex timing channels, novel detection and prevention techniques are also being developed to counter them. In this article, we provide a detailed survey of timing channels broadly categorized into network timing channel, in which communicating entities are connected by a network, and in-system timing channel, in which the communicating entities are within a computing system. This survey builds on the last comprehensive survey by Zander et al. [2007] and considers all three canonical applications of timing channels, namely, covert communication, timing side channel, and network flow watermarking. We survey the theoretical foundations, the implementation, and the various detection and prevention techniques that have been reported in literature. Based on the analysis of the current literature, we discuss potential future research directions both in the design and application of timing channels and their detection and prevention techniques.

A Trusted Computing Architecture of Embedded System Based on Improved TPM

The Trusted Platform Module (TPM) currently used by PCs is not suitable for embedded systems, it is necessary to improve existing TPM. The paper proposes a trusted computing architecture with new TPM and the cryptographic system developed by China for the embedded system. The improved TPM consists of the Embedded System Trusted Cryptography Module (eTCM) and the Embedded System Trusted Platform Control Module (eTPCM), which are combined and implemented the TPM’s autonomous control, active defense, high-speed encryption/decryption and other function through its internal bus arbitration module and symmetric and asymmetric cryptographic engines to effectively protect the security of embedded system. In our improved TPM, a trusted measurement method with chain model and star type model is used. Finally, the improved TPM is designed by FPGA, and it is used to a trusted PDA to carry out experimental verification. Experiments show that the trusted architecture of the embedded system based on the improved TPM is efficient, reliable and secure.

SecureNoSQL: An approach for secure search of encrypted NoSQL databases in the public cloud

While many schemes have been proposed to search encrypted relational databases, less attention has been paid to NoSQL databases. In this paper we report on the design and the implementation of a security scheme called “SecureNoSQL” for searching encrypted cloud NoSQL databases. Our solution is one of the first efforts covering not only data confidentiality, but also the integrity of the datasets residing on a cloud server. In our system a secure proxy carries out the required transformations and the cloud server is not modified. The construction is applicable to all NoSQL data models and, in our experiments, we present its application to a Document-store data model. The contributions of this paper include: (1) a descriptive language based on a subset of JSON notations; (2) a tool to create and parse a security plan consisting of cryptographic modules, data elements, and mappings of cryptographic modules to the data fields; and (3) a query and data validation mechanism based on the security plan.

Secure Elliptic Curve Cryptography based RFID Authentication Schemes for Internet of Things

In medical field, patients generally need highly equipped systems because of their inability to access emergency systems. In such situation, high level of security must be ensured to prevent fatal medical errors. RFID technology is generally used in the medical environment. Applications of elliptic curve algorithm are considered and several cryptography modules are analyzed. Heavy weight schemes are considered to be highly secure. Security drawbacks have been analyzed in Godor and Imre scheme in terms of maximum delay and running time and improved encryption and decryption scheme has been proposed. The proposed algorithm has been simulated in Xilinx 14.5 ISE and worst case slack, running time and frequency has been analyzed.

THE METHODS OF ARTIFICIAL INTELLIGENCE FOR MALICIOUS APPLICATIONS DETECTION IN ANDROID OS

This paper presents and discusses a method for Android’s applications classification with the purpose of malware detection. Based on the application of an Artificial Immune System and Artificial Neural Networks we propose the “antivirus” system especially for Android system that can detect and block undesirable and malicious applications. This system can be characterized by self-adaption and self-evolution and can detect even unknown and previously unseen malicious applications. The proposed system is the part of our team’s big project named “Intelligent Cyber Defense System” that includes malware detection and classification module, intrusions detection and classification module, cloud security module and personal cryptography module. This paper contains the extended research that was presented during the IEEE 8th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS’2015) [1].

Efficient Electromagnetic Analysis for Cryptographic Module on the Frequency Domain

SUMMARYAn efficient analysis method in the frequency domain for the extraction of information under the degradation of signal‐to‐noise ratio (SNR) is proposed. When the electromagnetic emission from the cryptographic module on the hardware is analyzed, the electromagnetic fields caused by operation on the other modules interfere to the electromagnetic field from the cryptographic module. Therefore, the amount of the measured data required for the extraction of information under the condition of degraded SNR increases and the analysis for this increase in data needs additional computation time. In order to accelerate the analysis under the degradation of SNR, we focus on only the processing of analysis target data. Furthermore, the signal of information and noises is separated with the analysis on the frequency domain. The proposed method is examined through experiments.

Fundamental Study on a Mechanism of Faulty Outputs from Cryptographic Modules Due to IEMI

SUMMARYThis paper investigates the mechanism underlying faulty outputs from cryptographic modules due to intentional electromagnetic interference (IEMI), which causes information leakage in electronic devices without disrupting their functions or damaging their components. We show this fault mechanism through experiments using the faulty ciphertexts and pulse injection to a specific round in the encryption process. The experimental results indicate that faulty outputs from cryptographic modules are caused by setup time violation in the cryptographic module.

Efficient Energy Saving Cryptographic Techniques with Software Solution in Wireless Network

To reduce communication costs, to protect our data from eavesdropping and from unauthorized users, cryptographic algorithms are used. Cryptographic module has to be developed for combining the operation of compression and encryption synchronously on the file. The information file is preliminary processed and then converts into one intermediary form so that it can be compressed with better efficiency and security. In this paper an optimized approaching coding technique which deals with both the issues of size and security is introduced and characterized experimentally using the performance measurement approach java in which file of any data length can be practically compressed and encrypted using new encryption technique and a novel energy saving technique in wireless communication network with efficient hardware solution is presented. To improve the strength and capability of algorithms and to compress the transmitted data an intelligent and reversible conversion technique is applied.

An overview of hardware-level statistical power analysis attack countermeasures

While the cryptographic modules used in modern embedded systems may employ mathematically secure algorithms, an attacker may still be able to compromise the security of a design using side-channel analysis. Side-channel attacks use leaked information in order to make inferences regarding the value of the secret key used for encryption. Statistical power analysis attacks are a class of side-channel attack which target power consumption as a leakage vector and apply statistical analysis to collected traces. As these attacks have been proven to be effective on a variety of hardware implementations, there exists a corresponding body of research regarding countermeasures. This work examines several statistical power analysis attack countermeasures in the literature and groups them into three broad categories consisting of secure logic styles, alterations to existing functional modules, and the inclusion of additional modules designed to enhance security. While a variety of options are available to a designer, there will always be a corresponding trade-off in terms of overhead factors like additional power consumption and area. As such, this work seeks to document and classify several of the approaches presented in the literature in order to help designers better select a countermeasure suited to their needs.

INTEGRATION OF HARDWARE SECURITY MODULES INTO A DEEPLY EMBEDDED TLS STACK

The Transport Layer Security (TLS) protocol is a well-established standard for securing communication over insecure communication links, offering layer-4 VPN functionality. In the classical Internet TLS is widely used. With the advances of the Internet of Things (IoT) there is an increasing need to secure communication on resource-constrained embedded devices. On these devices, computation of complex cryptographic algorithms is difficult. Additionally, sensor nodes are physically exposed to attackers. Cryptographic acceleration and secure hardware security modules (HSMs) are possible solutions to these challenges. The usage of specialized cryptographic modules for TLS is not a new phenomenon. However, there are still few hardware security modules suitable for the use on microcontrollers in sensor networks. We therefore present an overview of HSM and TLS solutions along with sample implementations and share some recommendations how to combine both.

Computer design of nanocircuits for cryptographic engineering

Since the introduction of side-channel attacks, cryptographic devices have been highly susceptible to power and electromagnetic (EM) analysis attacks: because these attacks require only relatively inexpensive equipment’s. Most of cryptographic circuits are typically implemented in CMOS. There is a strong dependency between power consumption of circuits implemented based on this logic style and the data that is processed by the circuit. Due to the difference between input and output capacitances of CMOS-transistors, when the transistor switches on and off, different amount of current flows through the transistor and leads to different amount of power consumption when the transistor processes logic a “0” or logic “1”. Unless adequate countermeasures are implemented, side channel attacks allow an unauthorized person to reveal the private key of a cryptographic module. Countermeasure a novel logic approach to Quantum-dot Cellular Automata (QCA). The proposed logic takes advantage of low power consumption QCA together with complicated clocking circuits as a paradigm of nanotechnology advances in cryptography engineering.

THE METHODS OF ARTIFICIAL INTELLIGENCE FOR MALICIOUS APPLICATIONS DETECTION IN ANDROID OS

This paper presents and discusses a method for Android’s applications classification with the purpose of malware detection. Based on the application of an Artificial Immune System and Artificial Neural Networks we propose the “antivirus” system especially for Android system that can detect and block undesirable and malicious applications. This system can be characterized by self-adaption and self-evolution and can detect even unknown and previously unseen malicious applications. The proposed system is the part of our team’s big project named “Intelligent Cyber Defense System” that includes malware detection and classification module, intrusions detection and classification module, cloud security module and personal cryptography module. This paper contains the extended research that was presented during the IEEE 8th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS’2015) [1].

개인정보보호 관련 법령의 내용과 보안제품 분포간의 연관성 분석

ABSTRACT For the past few years, personal information breach incidents, great and small, occurred constantly. Accordingly, the Personal Information Protection related Ordinances are enacted and amend ed persistently, and the information security products also kee p advancing and developing in the same way. There are the certifi cation systems such as Common Criteria Evaluation and Validatio n(CC) and Korea Cryptographic Module Validation Program(KCMVP) for th e information security products. These are also strictly carrie d out. This paper analyzes and categorizes the 5 Personal Informa tion Protection related Ordinances in the aspects of technical protection measures by using key words. Here are the 5 related ordinances; ‘the Personal Information Protection Act’, ‘the Act on Promoti on of Information and Communications Network Utilization and Infor mation Protection, etc’, ‘the Act on the Protection, Use, Etc, of Location Information’, ‘the Use and Protection of Credit Inform ation Act’, and ‘the Electronic Financial Transactions Act.’ Mo reover, this study analyzes the association between the technical prote ction measures in the 5 relevant laws and the information secur ity products that are obtaining the CC Evaluation & Validation(CC) and the products that are now produced at KISIA’s member compan ies. Keywords: Personal Information Protection, CC, KCMVP, KISIA

Nanoscale CMOS battery cells for gate level on‐chip security designs

An efficient power analysis attack countermeasure at the transistor gate level using novel nanoscale CMOS battery cells in a decoupling-based technique is presented. The proposed CMOS battery cells are used as decoupling elements between the gates implementing a sensitive operation inside a cryptographic module and the power supply rail of the integrated circuit. As a result, the battery cells form an intermediate on-chip power storage element, providing a masked power supply point for gates that are on a critical security path. The circuitry of the battery cells and the gates are designed using 65 nm TSMC CMOS technology. A test system was simulated with an 8 bit XOR serving as a target operation for a correlation power analysis attack. A total of 16 battery cells, two per gate for complementary cycles, were created with 1.74 µm2 P-type MOS transistors serving as energy storage devices. Results showed that the test system offered protection at 10 000 traces.