Cross-coupled PMOS Research Articles

High performance level restoration circuits

Three high performance level restoration circuits are proposed, which outperform the existing level restoration circuits with cross-coupled PMOS, in terms of power dissipation and delay. The first configuration employs a back-bias scheme in order to eliminate the stand-by leakage caused by the low-swing input. The second one adopts a bootstrapping technique, in order to restore the low-swing signal, without dc power consumption. Finally, a level restoration circuit is proposed, based on the generation of a narrow zero-pulse, for properly controlling the output PMOS device. The presented level restoration circuits can be implemented in standard CMOS technologies. By simulating the proposed circuits on a low-swing interconnect scheme, a 60% power savings have been observed over the conventional full-swing case.

Simple reversible energy recovery logic using NMOS switch networks with cross-coupled PMOS pair

A simpler reversible energy recovery logic is proposed, called feedback RERL, based on the previously presented reversible energy recovery logic (RERL), which does not have any nonadiabatic losses.

Pass-transistor adiabatic logic using single power-clock supply

We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 /spl mu/ CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 /spl mu/ CMOS technology has been experimentally verified.