Cross-coupled PMOS Transistors Research Articles

Design and implementation of a 60–113 GHz down-conversion mixer in 90 nm CMOS

A 60–113 GHz down-conversion mixer in 90 nm CMOS is demonstrated. The mixer adopts an RL core IF load, which is based on the series of a peaking inductor (L) and a parallel combination of the cross-coupled PMOS transistors (CCPT) and the diode-connected NMOS transistors (DCNT), i.e. L-CCPT–DCNT-based core IF load. Conversion gain (CG) can be significantly enhanced due to the increase of load impedance. The bandwidth can be improved due to the inductive peaking effect of the RL core IF load. The mixer consumes 3.2 mW and achieves RF-port input reflection coefficient of − 10 to − 31.2 dB for 82.8–97.2 GHz. The mixer attains CG of 16.8 ± 1.5 dB for 60–113 GHz. The corresponding 3 dB CG bandwidth is 53 GHz. Moreover, for 70–100 GHz, the mixer achieves CG of 17.4–18.3 dB and LO-RF isolation of 39.2–54.4 dB, one of the best CG and LO-RF isolation results ever reported for down-conversion mixers around 77 GHz or 94 GHz. These prominent results indicate that the down-conversion mixer is suitable for 77 GHz automobile radar and 94 GHz imaging radar systems.

Design and Analysis of a 94-GHz CMOS Down-Conversion Mixer With CCPT-RL-Based IF Load

A low-power W-band gain-enhanced CMOS down-conversion mixer for millimeter-wave-to-baseband pulsed-radar receiver is presented. To enhance the equivalent load impedance while keeping the transconductance ( $\text{g}_{\mathrm {m}}$ ) of the RF $\text{g}_{\mathrm {m}}$ stage unchanged and achieving prominent IF bandwidth, we propose a novel core IF load, which is based on the parallel combination of the cross-coupled PMOS transistors (CCPT) and the series RL circuit (i.e., CCPT-RL-based core IF load). The down-conversion mixer comprises a double-balanced Gilbert-cell-based mixer core with an inductive-peaking current-bleeding RF $\text{g}_{\mathrm {m}}$ stage and a CCPT-RL-based core IF load, two elliptic baluns, and a source follower buffer. Compared with the traditional down-conversion mixer for direct conversion receiver, conversion gain (CG), and noise figure (NF) can be significantly enhanced. For 88~100 GHz, the mixer consumes 5 mW and achieves excellent RF-port input reflection coefficient ( ${S}_{11}$ ) of −9.6~−19.1 dB and LO-port input reflection coefficient ( ${S}_{22}$ ) of −5.5~−21.9 dB. In addition, the mixer achieves excellent CG of 11.8~14.6 dB, NF of 14.2~15.2 dB, and LO-RF isolation of 34.6~35.3 dB–one of the best CG, NF, and LO-RF isolation results ever reported for a W-band down-conversion mixer.

Fast and energy-efficient low-voltage level shifters

This paper presents two novel low-voltage level shifter designs: one based on cross-coupled PMOS transistors and the other using current mirror structure. These two level shifters are designed to address the problems of the existing state-of-the-art level shifters. Simulation at 65nm shows that both of the proposed level shifters achieve significantly better performance (up to 12×) and energy consumption (up to 8×) than the state-of-the-art level shifters with similar or less area consumption while operating from near-threshold to super-threshold region, making them optimal for level shifting in low-power systems with multiple scalable voltage domains.

A 13.56 MHz CMOS Active Rectifier With Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems

A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |VAC|. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm(2). For the proposed rectifier measured at |VAC| = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for RL=500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |VAC| ranges from 1.5 to 4 V for RL=500 Ω.

A noise immunity improved level shift structure for a 600 V HVIC

A novel level shift circuit featuring with high dV/dt noise immunity and improved negative VS capacity is proposed in this paper. Compared with the conventional structure, the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt. In addition, a differential noise cancellation circuit is proposed to enhance the noise immunity further. Meanwhile, the negative VS capacity is improved by unifying the detected reference voltage and the logic block's threshold voltage. A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.

A 0.35-μm CMOS cross-coupled complementary Colpitts voltage controlled oscillator

This article presents a differential cross-coupled complementary Colpitts CMOS voltage-controlled oscillator (VCO).The low phase noise CMOS VCO has been implemented with the TSMC 0.35-μm 2P4M CMOS technology and adopts a pair of cross-coupled PMOS transistors to achieve faster start-up oscillation. The VCO operates from 6.16 to 6.5 GHz with 5.3% tuning range. The measured phase noise at 1 MHz offset is −121.12 dBc/Hz at 6.417 GHz. The power consumption of the VCO core is 6.16 mW. The figure of merit is −189.37 dBc/Hz. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26192

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm2. The BICS occupies only 41×17 μm2 of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.

Energy Efficient Charge Recovery for Positive Feedback Adiabatic Logic

This paper proposes an efficient charge recovery positive feedback adiabatic logic (PFAL). In the proposed technique (IPFAL), the original PFAL is modified so as to include an additional charge recovery path in parallel to the cross coupled PMOS transistors. PFAL is proved to be energy efficient among adiabatic logic families. Complex logic gates were developed using IPFAL and simulated using 3.3 V, 0.18ìm, CMOS technology. The simulation results show that the proposed technique reduces the power by more than 15% as compared to the other adiabatic logics particularly PFAL for basic inverter. The circuits were found to be functional beyond a power clock frequency of 800 MHz with negligible area overhead. To illustrate the energy recovery current waveforms are also given for the IPFAL Inverter at 600 MHz. This technique is also verified by applying it to a number of ISCAS benchmark circuits. Results prove that the maximum power saving is around 80% in IPFAL when compared to static CMOS.