Energy Efficient Charge Recovery for Positive Feedback Adiabatic Logic

Abstract

This paper proposes an efficient charge recovery positive feedback adiabatic logic (PFAL). In the proposed technique (IPFAL), the original PFAL is modified so as to include an additional charge recovery path in parallel to the cross coupled PMOS transistors. PFAL is proved to be energy efficient among adiabatic logic families. Complex logic gates were developed using IPFAL and simulated using 3.3 V, 0.18ìm, CMOS technology. The simulation results show that the proposed technique reduces the power by more than 15% as compared to the other adiabatic logics particularly PFAL for basic inverter. The circuits were found to be functional beyond a power clock frequency of 800 MHz with negligible area overhead. To illustrate the energy recovery current waveforms are also given for the IPFAL Inverter at 600 MHz. This technique is also verified by applying it to a number of ISCAS benchmark circuits. Results prove that the maximum power saving is around 80% in IPFAL when compared to static CMOS.