Crossbar Array Research Articles

Vertical Memristive Crossbar Array for Multilayer Graph Embedding and Analysis.

Graph data structures effectively represent objects and their relationships, enabling the modeling of complex connections in various fields. Recent work demonstrate that metal at diagonal crossbar arrays (m-CBA) can effectively represent planar graphs. However, they are unsuitable for representing multilayer graphs having multiple relationships across different layers. Using conventional software, embedding multilayer graphs in high-dimensional Euclidean spaces introduces significant mathematical complexity and computational burden, often resulting in information loss. This study proposes a unique graph embedding (mapping) method utilizing a fabricated vertical m-CBA (vm-CBA), where a custom-built measurement system thoroughly validated its functionality. This structure directly maps multilayer graphs into a 3D vm-CBA, accurately representing inter-layer and intra-layer connections. The practical link prediction and information scores across various real-world datasets demonstrated that vm-CBA achieved enhanced accuracy compared to conventional embeddings, even with a significantly decreased number of operations.

Error-Aware Training for In-RRAM Computing Design Considering Non-Ideal Effects in RRAM Crossbar Array and Peripheral Circuits

In recent years, computing in-memory (CIM) technology has been proposed to solve the bottleneck of data movement in AI edge designs. In-RRAM computing (IRC) is a popular architecture due to its low leakage current and high density. However, to integrate some simple computation in memory, the IRC designs often adopt analog operations, which bring new issues to the computation accuracy. In order to speed up the verification of computation results, an accurate behavioral model for the RRAM crossbar array and the peripheral circuits with non-ideal effects are proposed. By using the proposed behavioral model, we build a hierarchical simulation framework for IRC system to provide run-time errors for circuit design optimization and CNN training. As shown in the experimental results, the simulation accuracy of IRC system is greatly improved by considering the contribution from peripheral circuits, but the simulation time can be reduced from several hours to one minute. The error-aware CNN training with the proposed models efficiently improves the CNN inference accuracy in real applications, which solves the accuracy and efficiency issues in traditional approaches.

Research Progress of Neuromorphic Chips

The increasing amount of data in the era of artificial intelligence imposes higher demands on the computational power of neural networks, and in order to fulfill this demand, there is a pressing need to overcome the limitations imposed by the von Neumann architecture's memory wall. Memristors, with their characteristics, are considered the optimal electronic devices for implementing neuromorphic computing. Therefore, in order to better utilize memristors for the design and research of neuromorphic chips, this paper summarizes and comparatively analyzes the memristor characteristics, the RRAM basic principles, memristor array research, crossbar array designs based on memristors, and the study of memristor-based neuromorphic computing chips through the review. The paper emphasizes the challenges that memristor-based neuromorphic computing chips still face in the future, such as non-linear resistance variation. In addition, potential future research directions for amnesia-based neuromorphic computing chips, including amnesia architecture, programming techniques, and instruction set development, are discussed and investigated

Efficient scaling of large language models with mixture of experts and 3D analog in-memory computing.

Large language models (LLMs), with their remarkable generative capacities, have greatly impacted a range of fields, but they face scalability challenges due to their large parameter counts, which result in high costs for training and inference. The trend of increasing model sizes is exacerbating these challenges, particularly in terms of memory footprint, latency and energy consumption. Here we explore the deployment of 'mixture of experts' (MoEs) networks-networks that use conditional computing to keep computational demands low despite having many parameters-on three-dimensional (3D) non-volatile memory (NVM)-based analog in-memory computing (AIMC) hardware. When combined with the MoE architecture, this hardware, utilizing stacked NVM devices arranged in a crossbar array, offers a solution to the parameter-fetching bottleneck typical in traditional models deployed on conventional von-Neumann-based architectures. By simulating the deployment of MoEs on an abstract 3D AIMC system, we demonstrate that, due to their conditional compute mechanism, MoEs are inherently better suited to this hardware than conventional, dense model architectures. Our findings suggest that MoEs, in conjunction with emerging 3D NVM-based AIMC, can substantially reduce the inference costs of state-of-the-art LLMs, making them more accessible and energy-efficient.

In-memory encryption using the advanced encryption standard.

Encryption and decryption of data with very low latency and high energy efficiency is desirable in almost every application that deals with sensitive data. The advanced encryption standard (AES) is a widely adopted algorithm in symmetric key cryptography with numerous efficient implementations. Nonetheless, in scenarios involving extensive data processing, the primary limitations on performance and efficiency arise from data movement between memory and the processor, rather than data processing itself. In this article, we present a novel in-memory computing (IMC) approach for AES encryption and key-expansion, and experimentally validate it on an IMC prototype chip based on phase-change memory (PCM) technology. We leverage operators stored in PCM crossbar arrays to achieve the flexibility to tune performance at runtime based on the amount of free storage available in the memory system. In addition, we introduce a method for parallel in-memory polynomial modular multiplication and evaluate the potential of intrinsic stochastic properties of PCM devices for random key generation. We show how to further improve efficiency with minimal additional auxiliary circuitry. To evaluate the performance within a custom-built large-scale in-memory AES system, we design and implement a cycle-accurate simulator that integrates parameters from Spice simulations for detailed latency and energy consumption analysis of the AES algorithm. Our evaluations indicate that our IMC-based AES approach outperforms state-of-the-art methods, achieving speed factor improvements of up to 19.7 at equivalent energy efficiency.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

Capacitive Crossbar Array for Solving Matrix Equations in One-Shot

Capacitive Crossbar Array for Solving Matrix Equations in One-Shot

WAGONN: Weight Bit Agglomeration in Crossbar Arrays for Reduced Impact of Interconnect Resistance on DNN Inference Accuracy

WAGONN: Weight Bit Agglomeration in Crossbar Arrays for Reduced Impact of Interconnect Resistance on DNN Inference Accuracy

Memristive ternary Łukasiewicz logic based on reading-based ratioed resistive states (3R).

The thirst for more efficient computational paradigms has reignited interest in computation in memory (CIM), a burgeoning topic that pivots on the strengths of more versatile logic systems. Surging ahead in this innovative milieu, multi-valued logic systems have been identified as possessing the potential to amplify storage density and computation efficacy. Notably, ternary logic has attracted widespread research owing to its relatively lower computational and storage complexity, offering a promising alternative to the traditional binary logic computation. This study provides insight into the feasibility of ternary logic in the CIM domain using resistive random-access memory (ReRAM) devices. Its multi-level programming capability making it an ideal conduit for the integration of ternary logic. We focus on ternary Łukasiewicz logic because its computational characteristics are highly suitable for mapping logic values with input and output signals. This approach is characterized by voltage-reading-based output for ease of subsequent utilization and computation and validated in 1T1R crossbar arrays in an integrated ReRAM chip (Memory Advanced Demonstrator 200 mm). In addition, the effect of variability of memristive devices on logical computation and the potential for parallel operation are also investigated.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

Pt/ZrOx/Al2O3/TiN self-rectifying memristor crossbar array based on synergistic effect of interface barrier modulation and oxygen vacancy migration

Pt/ZrOx/Al2O3/TiN self-rectifying memristor crossbar array based on synergistic effect of interface barrier modulation and oxygen vacancy migration

Demonstration of a novel majority logic in a memristive crossbar array for in-memory parallel computing.

A memristive crossbar array can execute Boolean logic operations directly within the memory, which is highly noteworthy as it addresses the data bottleneck issue in traditional von Neumann computing. Although its potential has been widely demonstrated, achieving practical levels of operational reliability and computational efficiency remains a challenge. Here, we introduce a three-input majority logic gate supported by near-memory operations, serving as a universal gate and achieving both robust reliability and high efficiency in versatile logic operations. We fabricated a highly reliable HfOx-based memristive array, incorporating a series resistor to increase the reset voltage of the memristor, thereby increasing the operational voltage margin of the gate operation. This ensured reliable operation of the majority gate, resulting in successful experimental proof of combined 1-bit full adder and subtractor operations performed in 5 steps using 7 cells. Additionally, we propose that an N-bit parallel prefix adder (PPA) operation is possible in O(log2 N) steps, by taking advantage of the parallel operation capability of the majority gate. This achieves 8.5× higher spatiotemporal efficiency than the previously reported NOR-based logic system in 64-bit adder operation. Moreover, as N increases, the spatiotemporal efficiency further improves, which significantly enhances the applicability of memristive logic-in-memory.

Pixel‐Level Hardware Strategy for Large‐Scale Convolution Calculation in Neuromorphic Devices

AbstractFor convolution neural networks, increasing the performance of hardware computer systems is crucial in the era of big data. Benefiting from the neuromorphic devices, producing the convolutional calculation at the crossbar array circuit has become a promising approach for high‐performance hardware computer systems. However, as computation scales, this hardware system faces the challenge of low resource utilization efficiency and low power efficiency. Here, a novel pixel‐level strategy, leveraging the dynamic change of electron concentration as the process of convolution calculation, is proposed for high‐performance hardware computer systems. Compared with the crossbar array circuit‐based strategy, instead of at least four devices, raised the power efficiency to 413% and decreased the training epochs to 38%. This work presents a novel physics‐based approach that enables highly efficient convolutional calculation, improves power efficiency, speeds up convergency, and paves the way for building complex convolution neural networks with large‐scale convolutional computation capabilities.

Chiroptical Synaptic Perovskite Memristor as Reconfigurable Physical Unclonable Functions.

Physical unclonable functions (PUFs), often referred to as digital fingerprints, are emerging as critical elements in enhancing hardware security and encryption. While significant progress has been made in developing optical and memory-based PUFs, integrating reconfigurability with sensitivity to circularly polarized light (CPL) remains largely unexplored. Here, we present a chiroptical synaptic memristor (CSM) as a reconfigurable PUF, leveraging a two-dimensional organic-inorganic halide chiral perovskite. The device combines CPL sensitivity with photoresponsive electrical behavior, enabling its application in optoneuromorphic systems, as demonstrated by its ability to perform image categorization tasks within neuromorphic computing. Furthermore, by leveraging a 10 × 10 crossbar array of the CSMs, we develop a PUF capable of generating reconfigurable cryptographic keys based on the combination of neuromorphic potentiation and polarized light conditions. This work demonstrates an integrated approach to optoneuromorphic functionality, data storage, and encryption, providing an alternative approach for reconfigurable memristor-based PUFs.

Enhancing the Capacitive Memory Window of HZO FeCap Through Nanolaminate Stack Design

AbstractRecently, a capacitive array based on Hf0.5Zr0.5O2 (HZO) has been proposed as an alternative to conventional resistive crossbar arrays for compute‐in‐memory (CIM). This array operates through a capacitive memory window (CMWε). This arises due to interface asymmetry caused by varying defect densities at the top and bottom interfaces. However, the current CMWε is insufficient, necessitating strategies to enhance it. In this study, the impact of stack design on CMWε is examined and it is demonstrated that it is possible to precisely control critical fields in I–V curves to achieve a significantly higher CMWε. A record high CMWε is achieved through an innovative nanolaminate design. The observed characteristics are explained by the Landau‐Ginzburg‐Devonshire (LGD) model and the presence of extra critical fields during I–V sweep. The final device exhibits excellent uniformity and high‐speed operation. Additionally, a substantial memory window for a non‐destructive read operation (NDRO) is confirmed using AC pulses. Alongside detailed electrical characterization, TEM and XRD analyses for an in‐depth investigation is employed to uncover the root cause of the superior characteristics achieved. Ultimately, for analog vector‐matrix multiplication (VMM) in a capacitive array, the carefully designed nanolaminate stack significantly outperforms HZO (0.5) in both output voltage and voltage swing.

Two-Terminal Neuromorphic Devices for Spiking Neural Networks: Neurons, Synapses, and Array Integration.

The ever-increasing volume of complex data poses significant challenges to conventional sequential global processing methods, highlighting their inherent limitations. This computational burden has catalyzed interest in neuromorphic computing, particularly within artificial neural networks (ANNs). In pursuit of advancing neuromorphic hardware, researchers are focusing on developing computation strategies and constructing high-density crossbar arrays utilizing history-dependent, multistate nonvolatile memories tailored for multiply-accumulate (MAC) operations. However, the real-time collection and processing of massive, dynamic data sets require an innovative computational paradigm akin to that of the human brain. Spiking neural networks (SNNs), representing the third generation of ANNs, are emerging as a promising solution for real-time spatiotemporal information processing due to their event-based spatiotemporal capabilities. The ideal hardware supporting SNN operations comprises artificial neurons, artificial synapses, and their integrated arrays. Currently, the structural complexity of SNNs and spike-based methodologies requires hardware components with biomimetic behaviors that are distinct from those of conventional memristors used in deep neural networks. These distinctive characteristics required for neuron and synapses devices pose significant challenges. Developing effective building blocks for SNNs, therefore, necessitates leveraging the intrinsic properties of the materials constituting each unit and overcoming the integration barriers. This review focuses on the progress toward memristor-based spiking neural network neuromorphic hardware, emphasizing the role of individual components such as memristor-based neurons, synapses, and array integration along with relevant biological insights. We aim to provide valuable perspectives to researchers working on the next generation of brain-like computing systems based on these foundational elements.

Fully Resistive In‐Memory Cryptographic Engine with Dual‐Polarity Memristive Crossbar Array

AbstractAs data volume and complexity increase, conventional software‐based encryption methods face significant challenges, including vulnerability to attacks and high computational demands. This study proposes a hardware‐based cryptographic engine using a dual‐polarity memristive crossbar array with Ta/HfO2/RuO2 memristors, utilizing stochastic and deterministic operations for enhanced security and efficiency. The system integrates random key generation and XOR‐based logic operations within the memristive array, enabling robust encryption and decryption of binary data with a fully resistive data representation. Experimental validation of alphabet image data encryption and the array scale simulation of individual fingerprint authentication are conducted to validate the robustness of the proposed hardware and cryptographic method. The results demonstrate the potential of the proposed hardware for homomorphic encryption, enabling secure data processing without decryption, which can pave the way for memristive hardware to evolve into resistance‐based digital computing hardware.

Signal Integrity Analysis for Resistive Random Access Memory Crossbar Array by Compact Model With Consideration of Electro-Thermal Coupling Effects

Signal Integrity Analysis for Resistive Random Access Memory Crossbar Array by Compact Model With Consideration of Electro-Thermal Coupling Effects

Visualization of conductive filaments in TaOx-based ReRAM devices and investigation of their evolution during cycling by EBIC

Despite the great interest to the resistively switching devices (RS) as the potential candidates to solve the information process challenges arising so far, there is still a lack of the simple way to visualize the structural peculiarities underlying the RS device performance. In this work, we introduce and explain the exceptional sensitivity of the electron beam-induced current (EBIC) technique, realized in the scanning electron microscope, to the essential steps of Pt/TaOx/Ta devices operation with filamentary RS. We showed the possibility of visualizing conducting filaments (CFs) and monitoring changes in their number and sizes during the operation of Pt/TaOx/Ta memory cells. By EBIC, we confirmed the multi-filamentary mechanism of RS in the Pt/TaOx/Ta cells and established the patterns of CFs formation in the devices with the cross-bars topology, which may be helpful for the understanding of the performance peculiarities of the high-density cross-bar memory arrays.

Transparent Zinc Oxide Memristor Structures: Magnetron Sputtering of Thin Films, Resistive Switching Investigation, and Crossbar Array Fabrication.

This paper presents the results of experimental studies of the influence of high-frequency magnetron sputtering power on the structural and electrophysical properties of nanocrystalline ZnO films. It is shown that at a magnetron sputtering power of 75 W in an argon atmosphere at room temperature, ZnO films have a relatively smooth surface and a uniform nanocrystalline structure. Based on the results obtained, the formation and study of resistive switching of transparent ITO/ZnO/ITO memristor structures as well as a crossbar array based on them were performed. It is demonstrated that memristor structures based on ZnO films obtained at a magnetron sputtering power of 75 W exhibit stable resistive switching for 1000 cycles between high resistance states (HRS = 537.4 ± 26.7 Ω) and low resistance states (LRS = 291.4 ± 38.5 Ω), while the resistance ratio in HRS/LRS is ~1.8. On the basis of the experimental findings, we carried out mathematical modeling of the resistive switching of this structure, and it demonstrated that the regions with an increase in the electric field strength along the edge of the upper electrode become the main sources of oxygen vacancy generation in ZnO film. A crossbar array of 16 transparent ITO/ZnO/ITO memristor structures was also fabricated, demonstrating 20,000 resistive switching cycles between LRS = 13.8 ± 1.4 kΩ and HRS = 34.8 ± 2.6 kΩ for all devices, with a resistance ratio of HRS/LRS of ~2.5. The obtained results can be used in the development of technological processes for the manufacturing of transparent memristor crossbars for neuromorphic structures of machine vision, robotics, and artificial intelligence systems.

A generic volatile memristor model

Abstract A novel class of memristive devices that are volatile has recently emerged. These volatile memristors have proved advantageous in numerous applications, such as their use as selector devices for memristive crossbar arrays, circuit elements for spiking neurons and short-term synapses. Compact models that accurately describe their characteristics are necessary to reap the benefits of these devices. This paper proposes a generic compact volatile memristor model with parameters that can be adapted to various volatile memristive devices. These parameters can easily be used to tune the I-V characteristics as well as the temporal characteristics in terms of the delay and relaxation times. This work introduces two variants of the model, one for voltage-controlled devices and the other for current-controlled devices. The voltage-controlled variant of the model was fitted to an Ag-based filamentary volatile memristor, while the current-controlled variant was fitted to a Mott memristor. An extensive comparison of the fitted models to the experimental data has been provided. It has been shown that the proposed model can accurately describe the quasi-static I-V characteristics and temporal characteristics of both devices under various conditions.

(Invited) 2-Dimensional Halide Perovskite Memristors for Data Storage and Neuromorphic Computing

Halide perovskites, fascinating memristive materials owing to mixed ionic-electronic conductivity, have been attracting great attention as nonvolatile data storage and artificial synapses recently. However, polycrystalline nature in thin film form and instability under ambient air hamper them to be implemented in demonstrating reliable electronic devices. We successfully fabricated vertically aligned 2D halide perovskite films (V-HPs) for active layers of ReRAM and artificial synapses, showing moisture stability. Unlike random-oriented HPs, which exhibit negligible current hysteresis, V-HPs with Ag top electrodes exhibited highly stable and reliable binary memory performance. We built a flexible crossbar array to verify data storage capability, achieving a high (~100 %) device yield, robust endurance (5 × 106 cycles), long retention (2 × 105 s), reliability to operate under bending conditions, and moisture stability over a year. V-HPs with Au top electrodes showed multilevel analog memristive characteristics, programmable potentiation and depression with distinguished multi-states, long-short-term plasticity, paired-pulse facilitation, and even spike-timing-dependent plasticity. Our findings provide material design strategy that can be extended to the development of new semiconductor materials for next-generation memory devices.