Increase In Critical Path Delay Research Articles

An evolutionary approach to implement logic circuits on three dimensional FPGAs

Three Dimensional Field Programmable Gate Arrays (3D FPGAs) recently are presented as the next generation of the FPGA family to continue the integration of more transistors on a single chip seamlessly. The 3D FPGA are fabricated by stacking several layers of semiconductor substrates and the interconnection among layers are realized using Through Silicon Vias (TSVs). Despite their benefits regarding less area and higher speed, 3D FPGAs encounter two major problems; huge size of single TSV and trapping generated heat in inner layers. To handle these problems, we propose a complete Computer Aided Design (CAD) flow to implement an arbitrary logic circuit on 3D FPGA. Prtitioning, Placement, and Routing are primary stages of the proposed CAD flow. The partitioning and placement stages of the flow are based on Simulated Annealing algorithm. Furthermore, the routing stage is a modified version of the Pathfinder algorithm. Unbalanced SA based partitioning tremendously reduces the required TSVs along with distribution of highly active circuit’s modules on the bottom layers and constructing thermal channels facilitate transferring the generated heat in intermediate layers. Simulation results show more than 60%, 65%, and 23% reduction in TSV count, heat transfer performance, and area respectively, along with 4% increase in critical path delay. In addition, comparison between 2D FPGA and 3D FPGA with our proposed architecture (including 2 tier), shows that the circuit speed increases by 28.61%, and minimum channel width decreases by 30.47%. Finally, the results of comparison between 2-tier and 4-tier in 3D FPGA show that circuit speed and minimum channel width increase by 15.95% and 15.92% in 4-tier, respectively.

Reconfiguration-Based VLSI Design for Security

Reconfigurable computing is a critical technology for achieving nanoelectronic systems of yield and reliability. In this paper, we present that reconfigurable computing is further a critical technology for achieving hardware security in the presence of supply chain adversaries. Specifically, reconfigurable implementation of a given logic function achieves design obfuscation, while reconfiguration for difference logic functions further achieves moving target defense. We further present reconfigurable reversible computing-based cryptography, and a generic reconfiguration-based VLSI design-for-security methodology. In our case studies based on a SPARC V8 LEON2 processor, we prevent software- or hardware-based code injection attacks at cost of 0.72% area increase, negligible power consumption increase and no performance degradation; we further prevent a hardware Trojan from gaining unauthorized memory access at cost of 4.42% area increase, negligible power consumption increase, and 11.30% critical path delay increase.

Combined Architecture/Algorithm Approach to Fast FPGA Routing

We propose a new field-programmable gate array (FPGA) routing approach, which, when combined with a low-cost architecture change, results in a 40% reduction in router runtime, at the cost of a 6% area overhead and with no increase in critical path delay. Our approach begins with PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where the signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. We explore approximately 165 000 FPGA switch block architectures, showing that the choice of the architecture has a significant impact on the complexity of the SAT formulation, and by extension, on routing runtime. Our approach points to a new research direction, namely, reducing FPGA computer-aided design runtime by exploring FPGA architectures and algorithms together.

Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs

This article introduces a novel lookup table (LUT) and its usage in the configurable logic block (CLB) architectures for SRAM-based field-programmable gate array (FPGA) architectures. The proposed CLB allows sharing of SRAM tables of LUTs among NPN-equivalent functions to reduce the size of memories used for storing the functions and also reduces the number of configuration bits required. We measured many different characteristics of FPGAs using our new CLB architecture, including area, delay, routing, and power requirements. We experimentally found that for many different FPGA architectures, CLBs can share one-fourth of their SRAM tables between two basic logic elements (BLEs), which reduced both power consumption and area without negatively affecting routing or wirelength, and there was only a negligible increase in critical path delay of 0.27%. Specifically, we find that FPGAs consisting of CLBs with 16 BLEs and 34 inputs can be implemented with eight normal SRAMs and four SRAMs shared between two BLEs, for an overall reduction of four out of sixteen SRAM tables per CLB. With this new CLB architecture, we measured an approximate reduction in overall power consumption of 2% and an estimated reduction in area of 3%

Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits

This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reduction in the number of test vectors required to detect faults in VLSI circuits. The algorithm is based on the circuit's maximum primary input cone size ( N) and minimum fanout ( F) values to decide the location and number of partitions. Particle swarm optimization (PSO) is used to determine the optimal values of N and F to minimize the number of test vectors, the number of partitions, and the increase in critical path delay due to the added partitions. The proposed algorithm has been applied to the ISCAS’85 benchmark circuits and the results are compared to other partitioning approaches, showing that the PSO partitioning algorithm produces similar results, approximately one-order of magnitude faster.

Reducing switching activity on datapath buses with control-signal gating

This paper presents a technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on buses. The focus of the technique is on achieving effective power savings with minimal overhead. When a bus is not going to be used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. The observability don't-care of a bus is defined to detect unnecessary switching activity on the bus. This condition is used to gate control signals going to the bus-driver modules so that switching activity on the module inputs does not propagate to the bus. A methodology for automatically synthesizing gated control signals from the register transfer level description of a design is presented. The technique has very low area, delay, power, and designer effort overhead. It was applied to one of the integer execution units of a 64-bit, two-way superscalar RISC microprocessor. Experimental results from running various application programs on the microprocessor show an average of 26.6% reduction in dynamic switching power in the execution unit, with no increase in critical path delay and negligible area overhead.