Critical Dimension Difference Research Articles

New method of optimizing writing parameters in electron beam lithography systems for throughput improvement considering patterning fidelity constraints

Low-energy electron beam lithography is one of the promising next-generation lithography technology solutions for the 21-nm half-pitch node and beyond because of fewer proximity effects, higher resist sensitivity, and less substrate damage compared with high-energy electron beam lithography. To achieve high-throughput manufacturing, low-energy electron beam lithography systems with writing parameters of larger beam size, larger grid size, and lower dosage are preferred. However, electron shot noise can significantly increase critical dimension deviation and line edge roughness. Its influence on patterning prediction accuracy becomes nonnegligible. To effectively maximize throughput while meeting patterning fidelity requirements according to the International Technology Roadmap for Semiconductors, a new method is proposed in this work that utilizes a new patterning prediction algorithm to rigorously characterize the patterning variability caused by the shot noise and a mathematical optimization algorithm to determine optimal writing parameters. The new patterning prediction algorithm can achieve a proper trade-off between computational effort and patterning prediction accuracy. Effectiveness of the new method is demonstrated on a static random-access memory circuit. The corresponding electrical performance is analyzed by using a gate-slicing technique and publicly available transistor models. Numerical results show that a significant improvement in the static noise margin can be achieved.

Feedforward Run-to-Run Control for Reduced Parametric Transistor Variation in CMOS Logic 0.13 $\mu{\rm m}$ Technology

Targeting the physical gate Critical Dimension (CD) greatly impacts device performance. Unfortunately, advanced products within the CMOS logic 0.13 mum technology suffer from a large gate CD lot to lot variation, thereby causing large device parametric characteristics variability. A novel technique is to develop a feed-forward controller, which corrects for gate CD deviation by tuning the pocket implant dose (FFE-PI2). In order to enhance the controller robustness, a model-based Statistical Process Control (SPC) chart, and a new scatterometry grating have been considered. The FFE-PI2 control system is simulated and then implemented in STMicroelectronics 8Fab. Results indicate a significant decrease in lot to lot variation of transistor performance.

Investigation of Optimum Biasing and Undercut for Single Trench Alternating Phase Shift Mask in 193 nm Lithography

The use of an alternating phase shift mask is an effective method of improving resolution compared with binary and embedded attenuated phase shift mask technologies, but the intensity imbalance between the light propagating through the zero- and π-shifted spaces is the main obstacle to be overcome. Several technical methods are proposed to compensate for such an imbalance in the mask manufacturing process. The known general solutions for the intensity imbalance are applying a space bias and/or an undercut of the space region of the alternating phase shift mask. We evaluated the uniformity of the resist profile after the application of a space bias or an undercut of the mask space region in order to minimize the pattern position displacement and the critical dimension difference between the phase-shifted and unshifted regions for the 90 and 65 nm nodes. Additionally, we found that the imperfect side wall angle of an undercut or a space bias obviously affected the quality of pattern fidelity and hence investigated how the side wall angle affects pattern printability.

Shrinkage Process with Cure and Bake

Electron beam (EB) and ultraviolet (UV) have a curing effect on resist patterns. We found that high-temperature baking can shrink patterns cured using EB or vacuum ultraviolet (VUV). Critical dimension (CD) measurements were performed after baking. It was found that CD decreased with increasing baking temperature and the CD deviation after the postcure baking was almost the same as that of the initial pattern. Sub-100 nm line patterns were successfully fabricated by shrinking about 35 nm upon 350 °C postcure bake without pattern reflow. It was demonstrated that the CD shrinkage process has a high CD controllability due to the low dependence of shrinkage on baking temperature and the nondependence of shrinkage on pattern pitch, and the process does not influence CD deviation.

Photomask plasma etching: A review

Photomask plasma etching was thoroughly reviewed over wide topics including history, equipment, etchant, absorbers, phase shifters, thermodynamics, and kinetics. Plasma etch obtained industrial applications for photomask fabrication in the 1990s and presently is a critical fabrication step for the “enabling” photomask industry. Among all types of photomasks (binary, embedded attenuated phase-shift mask, and alternating aperture phase-shift mask), chromium (Cr) containing material etching has been the basis and fundamental for all photomask etches. The main technological challenges for Cr etch occur on (isolated) dark features of a high load photomask due to the etch critical dimension (CD) bias dependence on the local loading. It determines the CD features on the Cr layer, phase shifter MoSi layer, and fused silica (quartz) layer. The CD deviation on pattern layers from the nominal value has been a challenge, especially for the Cr state-of-the-art 65nm node photomasks even though data sizing exists. Inductively coupled plasma plus bias power using radio frequency wavelength is the dominant configuration of the photomask plasma etcher, with improved loading and CD mean-to-target potential. Thermodynamic applications (Gibbs energy minimization method) on photomask plasma etch provide a quick, easy, and low cost method to estimate the plasma etch feasibility and defect reduction at different plasma gas input conditions. Empirical relationships between operational parameters and etch properties significantly improve the only design of experiment procedure for etch process optimization.

Sensitivity-based conceptual design and tolerance allocation using the continuous ants colony algorithm (CACO)

In an assembly, there are two ways to control the deviation of critical dimensions. One is by keeping the deviation of the critical dimension small by tightening manufacturing tolerances and controlling aging and environmental effects. This approach is traditional and expensive, as it requires tighter manufacturing tolerances and protection from aging and the environment. The second is by moving the nominal values of the non-critical dimensions to a less sensitive portion. This approach is very helpful in improving the quality with no additional cost. One can analyze any number of designs very early in the concept development stage of a project. After the concept design the cost-based optimal tolerances for the corresponding dimensions are allocated. The continuous ants colony algorithm, a kind of meta-heuristic approach, is used as an optimization tool for minimizing the critical dimension deviation and allocating the cost- based optimal tolerances.

X-ray photoelectron spectroscopy investigation of sidewall passivation films formed during gate etch processes

We have used x-ray photoelectron spectroscopy (XPS) to investigate the composition of sidewall passivation films formed during the plasma patterning of 0.1 μm silicon gates in a high density plasma source, as a function of plasma operating conditions for HBr, Cl2, and O2 based chemistry. XPS analyses clearly show that sidewall passivation films SiXxOy (X=Br, Cl, x+2y⩽4) are formed during the main step of the gate etch process and become oxidized at the early stage of the overetch step leading to an oxidelike layer after halogen desorption. Sidewall passivation films are thicker under HBr based chemistry than under chlorine containing chemistries. In addition, the film thickness seems to be highly sensitive to oxygen dilution in HBr based plasma. These results are discussed in view of the critical dimension deviation budget bearable in sub-0.1 μm gate fabrication.

Effect of Basic Additives on Acid-Catalyzed Electron-Beam Negative Resist Using Intramolecular Dehydration of Phenylcarbinol

The effect of basic additives on a negative electron-beam resist utilizing acid-catalyzed intramolecular dehydration of 1,3,5-tris(2-(2-hydroxypropyl))benzene (Triol) was investigated. Quinoline was selected as the most effective additive to suppress acid-diffusion among investigated ones. Though the addition of quinoline decreased the Triol resist sensitivity, it enhanced the contrast and critical-dimension (CD) deviation stability to post-exposure-baking temperature variation. Optimized resist system achieved the CD deviation stability: 1.5 nm/°C and 100-nm line and space patterns with a dose of 6.2 µC/cm2 @ 50 kV. Influence of the additive on the Triol resist insolubilization mechanism was discussed.

Precise Control and Resizing of Polysilicon Gate Length by Hard-Mask Etching

In this paper, we describe the etching of hard SiON/SiN masks for the reactive ion etching (RIE) of gate polycrystalline silicon (polysilicon) to precisely control and reduce gate length in order to transcend the resolution limit of lithography. A mixture of C3F8 and oxygen is used to control gate length. To improve gate critical dimension (CD) accuracy in the wafer, radical etch rate during hard-mask etching is controlled by changing the electrode gap and the temperature distribution in the wafer. The amount of CD shift is successfully controlled by optimizing the oxygen flow rate without increasing its deviation. Consequently, a 0.24-µm-wide resist pattern can be successfully resized to a polysilicon gate electrode of 0.2 µm length. Moreover, etching of both hard-mask and polysilicon does not increase the CD deviation of the polysilicon gate electrode length at the least.

Performance of SR Lithography in Giga-bit DRAM Fabrication.

We have studied the characteristics of replicated resist pattern by synchrotron radiation (SR) lithography on the real topographic substrates such as a dynamic random access memory (DRAM) structure. Two type topographic structures; the step height between memory cell area and peripheral circuit area, which is regarded as the deviation of the mask/wafer gap and causes the difference of the optical image at each area, and small topographic structure in the memory cell area where the resist thickness changes continuously. It was found that the critical dimension (CD) was controlled within ±10% CD at the range of the proximity gap 14μm and a high contrast resist is effective to control the CD deviation in the memory cell area. On the real DRAM topographic structure at the height of 500A, we obtained the CD deviation of 0.014μm(3σ) for 0.14μm transfer gate pattern. These results show SR lithography is the promising technique for giga bit scale device fabrication.

Coulomb Interaction Effect in Cell Projection Lithography

In cell projection lithography, critical dimension (CD) control is one of the important issues for device fabrication as well as resolution. Because plural patterns are exposed in one shot under the same dose, the proximity effect correction is more difficult than in the conventional variable-shaped beam (VSB) lithography. We have analyzed the CD deviation in order to obtain high CD accuracy of less than 0.02 µ m (range) which is sufficient for manufacturing 1 G dynamic randam access memory (DRAM). We have found that the Coulomb interaction effect plays an important role in CD deviation. We have proposed a new exposure intensity distribution (EID) function which contains a factor introduced for the first time to compensate the proximity effect and the Coulomb interaction effect simultaneously. The results indicate that the new EID function is very effective to compensate the Coulomb interaction effect and improve the CD deviation from 12% (0.03 µ m) to 6% (0.015 µ m) for 0.25 µ m lines-and-spaces (L/S) patterns.

Effect of electron-beam parameters on critical-dimension measurements

In critical-dimension (CD) measurements of resist patterns, CD deviation dependent on measurement time and adjacent pattern effect are major problems created by using an electron beam. We studied the mechanism of these effects. The dependence of CD deviation on measurement time may be caused as a result of compound effects of resist thickening due to surface contamination and resist thinning due to electron-beam induced resist contraction. The adjacent pattern effect is mainly produced by surface charging. The surface charge may distort the electron-beam trajectory.

Highly accurate critical dimension measurement for sub-0.5-μm devices

In the measurement of patterned resists, deviation of the critical dimension (CD) is frequently observed. We have found that contamination on the resist on a Si wafer can degrade the static repeatability more than the charging phenomenon at low accelerating voltage (Vacc), that is, near 1 kV. We investigate the dependence of contamination rate (Rc) and the normalized yield of secondary electrons (δ′) on Vacc and emission current (Ie) in order to clarify the influence of the contamination and charging effects. Experimental results indicate that we can minimize the Rc by optimizing Vacc and Ie. The Rc change cannot be attributed only to the contamination and charging effects, however. It seems, instead, that two competitive reactions (deposition and etching) occur simultaneously during the measurement at low voltage. The etching effect can be interpreted as a dissociation reaction at the resist surface. To reduce the CD deviation and improve the accuracy of the CD measurement, the accelerating voltage and current density must be optimized. Doing so improves the static repeatability from 0.008 to 0.003 μm (3σ).