Flash lamp annealing (FLA) has been explored as an alternative to excimer laser annealed low-temperature polycrystalline silicon (LTPS) for display applications and has shown potential to streamline and decrease the cost of fabrication while maintaining electrical performance [1], [2]. In this method, amorphous silicon is exposed to a single pulse of light emitted from a xenon flash lamp, causing melting and recrystallization in an area of cm2 rather than nm2 in less than a millisecond. FLA has shown value in crystallizing silicon and activating dopants in both PFET and NFET thin-film transistors (TFTs) [3]. However, FLA suffers from inconsistent material uniformity, a consequence of large areas of silicon melting simultaneously. This can cause the molten silicon to de-wet from the oxide or nitride underlayer, leading to the formation of numerous randomized voids. Though previous studies have shown encouraging results when using this void-associated LTPS morphology, improved structure control is necessary to reduce the variance of FLA-LTPS device operation.Edge-directed LTPS has a distinctly different macroscopic morphology than the void associated material, with potential advantages in uniformity and electrical performance. Differences between these morphologies have been previously discussed [4], however in that work the realization of the edge-directed material was hardly intentional and the formation mechanism was not clearly determined. A repeatable and controllable method of producing edge-directed LTPS would effectively solve a key obstacle towards industrial integration of FLA, that of randomly-dispersed irregularities and material nonuniformity.In this work, a replicable morphology of FLA-LTPS is produced and analyzed by using a thin chromium underlayer to promote adhesion without rendering the silicon entirely conductive. With thickness reduced to < 10 nm, Cr does not absorb damaging amounts of energy from the FLA pulse, as opposed to other metal and ceramic layers, which could improve wettability. Chrome has been applied as a silicon underlayer in thin-film photovoltaic applications [5]. The result of this Cr adhesion layer beneath an a-Si mesa during FLA is a characteristic ridge-like pattern of grain formation, as shown in Figure 1A. Large, elongated domains oriented perpendicular to the edges of the silicon mesas are clearly visible. An abrupt ridge is seen equidistant between the long edges of this mesa, with further diagonal ridges present at a 45° angle from the corners. This structure suggests a propagation of crystallization that begins at the edge of the mesas and travels inwards, terminating when it reaches another advancing crystallization front. This structure is only realized when the Cr layer is a continuous film rather than discrete microparticles, suggesting that the effect is due to adhesion rather than metal-induced crystallization. Without this adhesion layer, the randomly-irregular structure seen in Figure 1B is produced. Figure 1C demonstrates atomic force microscopy on this ridge morphology. In this structure, a maximum height differential of around 55 nm between the tops of ridges and the lowest point on the mesa is demonstrated (ignoring scanning artifacts). This is significant, as the original thickness of amorphous silicon as deposited was only 60 nm, suggesting large-scale mass transfer during crystallization. However, dewetting behavior is minimized. The elongated structure, lack of voids, and edge-inward pattern of this morphology is hypothetically consistent with explosive crystallization [6], versus a quasi-equilibrium melt-phase which results in randomly-irregular material.Similar morphology has been demonstrated using excimer laser and continuous-wave laser annealing, in which only a small area of silicon is in liquid phase at any given moment [7], [8]. However, its formation in FLA, in which large areas are melted simultaneously, is an important step towards the commercial viability of flash lamp annealing. This polycrystalline material is being explored as a viable channel material for PFET TFTs. The apparent presence of micrometer-scale grains is expected to improve channel mobility [9], while providing a uniform and predictable structure, thus minimizing variance in device operation. Material properties and electrical characteristics will be presented. Figure 1
Read full abstract
Oct 2, 2024
Parnia Navabpour + 6
Open Access
